changelog spacing fix
[sven/mpt-status.git] / mpt-status.includes.patch
1 diff -Nur mpt-status-1.2.0.orig/includes/mpi_cnfg.h mpt-status-1.2.0/includes/mpi_cnfg.h
2 --- mpt-status-1.2.0.orig/includes/mpi_cnfg.h   1970-01-01 01:00:00.000000000 +0100
3 +++ mpt-status-1.2.0/includes/mpi_cnfg.h        2011-09-11 17:15:29.681901384 +0200
4 @@ -0,0 +1,2801 @@
5 +/*
6 + *  Copyright (c) 2000-2005 LSI Logic Corporation.
7 + *
8 + *
9 + *           Name:  mpi_cnfg.h
10 + *          Title:  MPI Config message, structures, and Pages
11 + *  Creation Date:  July 27, 2000
12 + *
13 + *    mpi_cnfg.h Version:  01.05.09
14 + *
15 + *  Version History
16 + *  ---------------
17 + *
18 + *  Date      Version   Description
19 + *  --------  --------  ------------------------------------------------------
20 + *  05-08-00  00.10.01  Original release for 0.10 spec dated 4/26/2000.
21 + *  06-06-00  01.00.01  Update version number for 1.0 release.
22 + *  06-08-00  01.00.02  Added _PAGEVERSION definitions for all pages.
23 + *                      Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
24 + *                      fields to FC_DEVICE_0 page, updated the page version.
25 + *                      Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
26 + *                      SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
27 + *                      and updated the page versions.
28 + *                      Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
29 + *                      page and updated the page version.
30 + *                      Added Information field and _INFO_PARAMS_NEGOTIATED
31 + *                      definitionto SCSI_DEVICE_0 page.
32 + *  06-22-00  01.00.03  Removed batch controls from LAN_0 page and updated the
33 + *                      page version.
34 + *                      Added BucketsRemaining to LAN_1 page, redefined the
35 + *                      state values, and updated the page version.
36 + *                      Revised bus width definitions in SCSI_PORT_0,
37 + *                      SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
38 + *  06-30-00  01.00.04  Added MaxReplySize to LAN_1 page and updated the page
39 + *                      version.
40 + *                      Moved FC_DEVICE_0 PageAddress description to spec.
41 + *  07-27-00  01.00.05  Corrected the SubsystemVendorID and SubsystemID field
42 + *                      widths in IOC_0 page and updated the page version.
43 + *  11-02-00  01.01.01  Original release for post 1.0 work
44 + *                      Added Manufacturing pages, IO Unit Page 2, SCSI SPI
45 + *                      Port Page 2, FC Port Page 4, FC Port Page 5
46 + *  11-15-00  01.01.02  Interim changes to match proposals
47 + *  12-04-00  01.01.03  Config page changes to match MPI rev 1.00.01.
48 + *  12-05-00  01.01.04  Modified config page actions.
49 + *  01-09-01  01.01.05  Added defines for page address formats.
50 + *                      Data size for Manufacturing pages 2 and 3 no longer
51 + *                      defined here.
52 + *                      Io Unit Page 2 size is fixed at 4 adapters and some
53 + *                      flags were changed.
54 + *                      SCSI Port Page 2 Device Settings modified.
55 + *                      New fields added to FC Port Page 0 and some flags
56 + *                      cleaned up.
57 + *                      Removed impedance flash from FC Port Page 1.
58 + *                      Added FC Port pages 6 and 7.
59 + *  01-25-01  01.01.06  Added MaxInitiators field to FcPortPage0.
60 + *  01-29-01  01.01.07  Changed some defines to make them 32 character unique.
61 + *                      Added some LinkType defines for FcPortPage0.
62 + *  02-20-01  01.01.08  Started using MPI_POINTER.
63 + *  02-27-01  01.01.09  Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
64 + *                      MPI_CONFIG_PAGETYPE_RAID_VOLUME.
65 + *                      Added definitions and structures for IOC Page 2 and
66 + *                      RAID Volume Page 2.
67 + *  03-27-01  01.01.10  Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
68 + *                      CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
69 + *                      Added VendorId and ProductRevLevel fields to
70 + *                      RAIDVOL2_IM_PHYS_ID struct.
71 + *                      Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
72 + *                      defines to make them compatible to MPI version 1.0.
73 + *                      Added structure offset comments.
74 + *  04-09-01  01.01.11  Added some new defines for the PageAddress field and
75 + *                      removed some obsolete ones.
76 + *                      Added IO Unit Page 3.
77 + *                      Modified defines for Scsi Port Page 2.
78 + *                      Modified RAID Volume Pages.
79 + *  08-08-01  01.02.01  Original release for v1.2 work.
80 + *                      Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
81 + *                      Added defines for the SEP bits in RVP2 VolumeSettings.
82 + *                      Modified the DeviceSettings field in RVP2 to use the
83 + *                      proper structure.
84 + *                      Added defines for SES, SAF-TE, and cross channel for
85 + *                      IOCPage2 CapabilitiesFlags.
86 + *                      Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
87 + *                      Removed define for
88 + *                      MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
89 + *                      Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
90 + *  08-29-01 01.02.02   Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
91 + *                      Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
92 + *                      and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
93 + *                      Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
94 + *                      MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
95 + *                      MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
96 + *                      MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
97 + *                      Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
98 + *                      and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
99 + *                      Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
100 + *                      Added rejected bits to SCSI Device Page 0 Information.
101 + *                      Increased size of ALPA array in FC Port Page 2 by one
102 + *                      and removed a one byte reserved field.
103 + *  09-28-01 01.02.03   Swapped NegWireSpeedLow and NegWireSpeedLow in
104 + *                      CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
105 + *                      Added structures for Manufacturing Page 4, IO Unit
106 + *                      Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
107 + *                      RAID PhysDisk Page 0.
108 + *  10-04-01 01.02.04   Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
109 + *                      Modified some of the new defines to make them 32
110 + *                      character unique.
111 + *                      Modified how variable length pages (arrays) are defined.
112 + *                      Added generic defines for hot spare pools and RAID
113 + *                      volume types.
114 + *  11-01-01 01.02.05   Added define for MPI_IOUNITPAGE1_DISABLE_IR.
115 + *  03-14-02 01.02.06   Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
116 + *                      related define, and bumped the page version define.
117 + *  05-31-02 01.02.07   Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
118 + *                      reserved byte and added a define.
119 + *                      Added define for
120 + *                      MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
121 + *                      Added new config page: CONFIG_PAGE_IOC_5.
122 + *                      Added MaxAliases, MaxHardAliases, and NumCurrentAliases
123 + *                      fields to CONFIG_PAGE_FC_PORT_0.
124 + *                      Added AltConnector and NumRequestedAliases fields to
125 + *                      CONFIG_PAGE_FC_PORT_1.
126 + *                      Added new config page: CONFIG_PAGE_FC_PORT_10.
127 + *  07-12-02 01.02.08   Added more MPI_MANUFACTPAGE_DEVID_ defines.
128 + *                      Added additional MPI_SCSIDEVPAGE0_NP_ defines.
129 + *                      Added more MPI_SCSIDEVPAGE1_RP_ defines.
130 + *                      Added define for
131 + *                      MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
132 + *                      Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
133 + *                      Modified MPI_FCPORTPAGE5_FLAGS_ defines.
134 + *  09-16-02 01.02.09   Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
135 + *  11-15-02 01.02.10   Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
136 + *                      Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
137 + *                      Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
138 + *  04-01-03 01.02.11   Added RR_TOV field and additional Flags defines for
139 + *                      CONFIG_PAGE_FC_PORT_1.
140 + *                      Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
141 + *                      an alias.
142 + *                      Added more device id defines.
143 + *  06-26-03 01.02.12   Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
144 + *                      Added TargetConfig and IDConfig fields to
145 + *                      CONFIG_PAGE_SCSI_PORT_1.
146 + *                      Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
147 + *                      to control DV.
148 + *                      Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
149 + *                      In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
150 + *                      with ADISCHardALPA.
151 + *                      Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
152 + *  01-16-04 01.02.13   Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
153 + *                      fields and related defines to CONFIG_PAGE_FC_PORT_1.
154 + *                      Added define for
155 + *                      MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
156 + *                      Added new fields to the substructures of
157 + *                      CONFIG_PAGE_FC_PORT_10.
158 + *  04-29-04 01.02.14   Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
159 + *                      CONFIG_PAGE_SCSI_DEVICE_0, and
160 + *                      CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
161 + *                      these pages.
162 + *  05-11-04 01.03.01   Added structure for CONFIG_PAGE_INBAND_0.
163 + *  08-19-04 01.05.01   Modified MSG_CONFIG request to support extended config
164 + *                      pages.
165 + *                      Added a new structure for extended config page header.
166 + *                      Added new extended config pages types and structures for
167 + *                      SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
168 + *                      Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
169 + *                      to add a Flags field.
170 + *                      Two new Manufacturing config pages (5 and 6).
171 + *                      Two new bits defined for IO Unit Page 1 Flags field.
172 + *                      Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
173 + *                      to specify the BIOS boot device.
174 + *                      Four new Flags bits defined for IO Unit Page 2.
175 + *                      Added IO Unit Page 4.
176 + *                      Added EEDP Flags settings to IOC Page 1.
177 + *                      Added new BIOS Page 1 config page.
178 + *  10-05-04 01.05.02   Added define for
179 + *                      MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
180 + *                      Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
181 + *                      associated defines.
182 + *                      Added more defines for SAS IO Unit Page 0
183 + *                      DiscoveryStatus field.
184 + *                      Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
185 + *                      and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
186 + *                      Added defines for Physical Mapping Modes to SAS IO Unit
187 + *                      Page 2.
188 + *                      Added define for
189 + *                      MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
190 + *  10-27-04 01.05.03   Added defines for new SAS PHY page addressing mode.
191 + *                      Added defines for MaxTargetSpinUp to BIOS Page 1.
192 + *                      Added 5 new ControlFlags defines for SAS IO Unit
193 + *                      Page 1.
194 + *                      Added MaxNumPhysicalMappedIDs field to SAS IO Unit
195 + *                      Page 2.
196 + *                      Added AccessStatus field to SAS Device Page 0 and added
197 + *                      new Flags bits for supported SATA features.
198 + *  12-07-04  01.05.04  Added config page structures for BIOS Page 2, RAID
199 + *                      Volume Page 1, and RAID Physical Disk Page 1.
200 + *                      Replaced IO Unit Page 1 BootTargetID,BootBus, and
201 + *                      BootAdapterNum with reserved field.
202 + *                      Added DataScrubRate and ResyncRate to RAID Volume
203 + *                      Page 0.
204 + *                      Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
205 + *                      define.
206 + *  12-09-04  01.05.05  Added Target Mode Large CDB Enable to FC Port Page 1
207 + *                      Flags field.
208 + *                      Added Auto Port Config flag define for SAS IOUNIT
209 + *                      Page 1 ControlFlags.
210 + *                      Added Disabled bad Phy define to Expander Page 1
211 + *                      Discovery Info field.
212 + *                      Added SAS/SATA device support to SAS IOUnit Page 1
213 + *                      ControlFlags.
214 + *                      Added Unsupported device to SAS Dev Page 0 Flags field
215 + *                      Added disable use SATA Hash Address for SAS IOUNIT
216 + *                      page 1 in ControlFields.
217 + *  01-15-05  01.05.06  Added defaults for data scrub rate and resync rate to
218 + *                      Manufacturing Page 4.
219 + *                      Added new defines for BIOS Page 1 IOCSettings field.
220 + *                      Added ExtDiskIdentifier field to RAID Physical Disk
221 + *                      Page 0.
222 + *                      Added new defines for SAS IO Unit Page 1 ControlFlags
223 + *                      and to SAS Device Page 0 Flags to control SATA devices.
224 + *                      Added defines and structures for the new Log Page 0, a
225 + *                      new type of configuration page.
226 + *  02-09-05  01.05.07  Added InactiveStatus field to RAID Volume Page 0.
227 + *                      Added WWID field to RAID Volume Page 1.
228 + *                      Added PhysicalPort field to SAS Expander pages 0 and 1.
229 + *  03-11-05  01.05.08  Removed the EEDP flags from IOC Page 1.
230 + *                      Added Enclosure/Slot boot device format to BIOS Page 2.
231 + *                      New status value for RAID Volume Page 0 VolumeStatus
232 + *                      (VolumeState subfield).
233 + *                      New value for RAID Physical Page 0 InactiveStatus.
234 + *                      Added Inactive Volume Member flag RAID Physical Disk
235 + *                      Page 0 PhysDiskStatus field.
236 + *                      New physical mapping mode in SAS IO Unit Page 2.
237 + *                      Added CONFIG_PAGE_SAS_ENCLOSURE_0.
238 + *                      Added Slot and Enclosure fields to SAS Device Page 0.
239 + *  06-24-05  01.05.09  Added EEDP defines to IOC Page 1.
240 + *                      Added more RAID type defines to IOC Page 2.
241 + *                      Added Port Enable Delay settings to BIOS Page 1.
242 + *                      Added Bad Block Table Full define to RAID Volume Page 0.
243 + *                      Added Previous State defines to RAID Physical Disk
244 + *                      Page 0.
245 + *                      Added Max Sata Targets define for DiscoveryStatus field
246 + *                      of SAS IO Unit Page 0.
247 + *                      Added Device Self Test to Control Flags of SAS IO Unit
248 + *                      Page 1.
249 + *                      Added Direct Attach Starting Slot Number define for SAS
250 + *                      IO Unit Page 2.
251 + *                      Added new fields in SAS Device Page 2 for enclosure
252 + *                      mapping.
253 + *                      Added OwnerDevHandle and Flags field to SAS PHY Page 0.
254 + *                      Added IOC GPIO Flags define to SAS Enclosure Page 0.
255 + *                      Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
256 + *  --------------------------------------------------------------------------
257 + */
258 +
259 +#ifndef MPI_CNFG_H
260 +#define MPI_CNFG_H
261 +
262 +
263 +/*****************************************************************************
264 +*
265 +*       C o n f i g    M e s s a g e    a n d    S t r u c t u r e s
266 +*
267 +*****************************************************************************/
268 +
269 +typedef struct _CONFIG_PAGE_HEADER
270 +{
271 +    U8                      PageVersion;                /* 00h */
272 +    U8                      PageLength;                 /* 01h */
273 +    U8                      PageNumber;                 /* 02h */
274 +    U8                      PageType;                   /* 03h */
275 +} CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
276 +  ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
277 +
278 +typedef union _CONFIG_PAGE_HEADER_UNION
279 +{
280 +   ConfigPageHeader_t  Struct;
281 +   U8                  Bytes[4];
282 +   U16                 Word16[2];
283 +   U32                 Word32;
284 +} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
285 +  CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
286 +
287 +typedef struct _CONFIG_EXTENDED_PAGE_HEADER
288 +{
289 +    U8                  PageVersion;                /* 00h */
290 +    U8                  Reserved1;                  /* 01h */
291 +    U8                  PageNumber;                 /* 02h */
292 +    U8                  PageType;                   /* 03h */
293 +    U16                 ExtPageLength;              /* 04h */
294 +    U8                  ExtPageType;                /* 06h */
295 +    U8                  Reserved2;                  /* 07h */
296 +} CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
297 +  ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
298 +
299 +
300 +
301 +/****************************************************************************
302 +*   PageType field values
303 +****************************************************************************/
304 +#define MPI_CONFIG_PAGEATTR_READ_ONLY               (0x00)
305 +#define MPI_CONFIG_PAGEATTR_CHANGEABLE              (0x10)
306 +#define MPI_CONFIG_PAGEATTR_PERSISTENT              (0x20)
307 +#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT           (0x30)
308 +#define MPI_CONFIG_PAGEATTR_MASK                    (0xF0)
309 +
310 +#define MPI_CONFIG_PAGETYPE_IO_UNIT                 (0x00)
311 +#define MPI_CONFIG_PAGETYPE_IOC                     (0x01)
312 +#define MPI_CONFIG_PAGETYPE_BIOS                    (0x02)
313 +#define MPI_CONFIG_PAGETYPE_SCSI_PORT               (0x03)
314 +#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE             (0x04)
315 +#define MPI_CONFIG_PAGETYPE_FC_PORT                 (0x05)
316 +#define MPI_CONFIG_PAGETYPE_FC_DEVICE               (0x06)
317 +#define MPI_CONFIG_PAGETYPE_LAN                     (0x07)
318 +#define MPI_CONFIG_PAGETYPE_RAID_VOLUME             (0x08)
319 +#define MPI_CONFIG_PAGETYPE_MANUFACTURING           (0x09)
320 +#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK           (0x0A)
321 +#define MPI_CONFIG_PAGETYPE_INBAND                  (0x0B)
322 +#define MPI_CONFIG_PAGETYPE_EXTENDED                (0x0F)
323 +#define MPI_CONFIG_PAGETYPE_MASK                    (0x0F)
324 +
325 +#define MPI_CONFIG_TYPENUM_MASK                     (0x0FFF)
326 +
327 +
328 +/****************************************************************************
329 +*   ExtPageType field values
330 +****************************************************************************/
331 +#define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT          (0x10)
332 +#define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER         (0x11)
333 +#define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE           (0x12)
334 +#define MPI_CONFIG_EXTPAGETYPE_SAS_PHY              (0x13)
335 +#define MPI_CONFIG_EXTPAGETYPE_LOG                  (0x14)
336 +#define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE            (0x15)
337 +
338 +
339 +/****************************************************************************
340 +*   PageAddress field values
341 +****************************************************************************/
342 +#define MPI_SCSI_PORT_PGAD_PORT_MASK                (0x000000FF)
343 +
344 +#define MPI_SCSI_DEVICE_FORM_MASK                   (0xF0000000)
345 +#define MPI_SCSI_DEVICE_FORM_BUS_TID                (0x00000000)
346 +#define MPI_SCSI_DEVICE_TARGET_ID_MASK              (0x000000FF)
347 +#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT             (0)
348 +#define MPI_SCSI_DEVICE_BUS_MASK                    (0x0000FF00)
349 +#define MPI_SCSI_DEVICE_BUS_SHIFT                   (8)
350 +#define MPI_SCSI_DEVICE_FORM_TARGET_MODE            (0x10000000)
351 +#define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK          (0x000000FF)
352 +#define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT         (0)
353 +#define MPI_SCSI_DEVICE_TM_BUS_MASK                 (0x0000FF00)
354 +#define MPI_SCSI_DEVICE_TM_BUS_SHIFT                (8)
355 +#define MPI_SCSI_DEVICE_TM_INIT_ID_MASK             (0x00FF0000)
356 +#define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT            (16)
357 +
358 +#define MPI_FC_PORT_PGAD_PORT_MASK                  (0xF0000000)
359 +#define MPI_FC_PORT_PGAD_PORT_SHIFT                 (28)
360 +#define MPI_FC_PORT_PGAD_FORM_MASK                  (0x0F000000)
361 +#define MPI_FC_PORT_PGAD_FORM_INDEX                 (0x01000000)
362 +#define MPI_FC_PORT_PGAD_INDEX_MASK                 (0x0000FFFF)
363 +#define MPI_FC_PORT_PGAD_INDEX_SHIFT                (0)
364 +
365 +#define MPI_FC_DEVICE_PGAD_PORT_MASK                (0xF0000000)
366 +#define MPI_FC_DEVICE_PGAD_PORT_SHIFT               (28)
367 +#define MPI_FC_DEVICE_PGAD_FORM_MASK                (0x0F000000)
368 +#define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID            (0x00000000)
369 +#define MPI_FC_DEVICE_PGAD_ND_PORT_MASK             (0xF0000000)
370 +#define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT            (28)
371 +#define MPI_FC_DEVICE_PGAD_ND_DID_MASK              (0x00FFFFFF)
372 +#define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT             (0)
373 +#define MPI_FC_DEVICE_PGAD_FORM_BUS_TID             (0x01000000)
374 +#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK              (0x0000FF00)
375 +#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT             (8)
376 +#define MPI_FC_DEVICE_PGAD_BT_TID_MASK              (0x000000FF)
377 +#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT             (0)
378 +
379 +#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK          (0x000000FF)
380 +#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT         (0)
381 +
382 +#define MPI_SAS_EXPAND_PGAD_FORM_MASK             (0xF0000000)
383 +#define MPI_SAS_EXPAND_PGAD_FORM_SHIFT            (28)
384 +#define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
385 +#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM   (0x00000001)
386 +#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE           (0x00000002)
387 +#define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE       (0x0000FFFF)
388 +#define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE      (0)
389 +#define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY          (0x00FF0000)
390 +#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY         (16)
391 +#define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE       (0x0000FFFF)
392 +#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE      (0)
393 +#define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE         (0x0000FFFF)
394 +#define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE        (0)
395 +
396 +#define MPI_SAS_DEVICE_PGAD_FORM_MASK               (0xF0000000)
397 +#define MPI_SAS_DEVICE_PGAD_FORM_SHIFT              (28)
398 +#define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE    (0x00000000)
399 +#define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID      (0x00000001)
400 +#define MPI_SAS_DEVICE_PGAD_FORM_HANDLE             (0x00000002)
401 +#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK         (0x0000FFFF)
402 +#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT        (0)
403 +#define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK             (0x0000FF00)
404 +#define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT            (8)
405 +#define MPI_SAS_DEVICE_PGAD_BT_TID_MASK             (0x000000FF)
406 +#define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT            (0)
407 +#define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK           (0x0000FFFF)
408 +#define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT          (0)
409 +
410 +#define MPI_SAS_PHY_PGAD_FORM_MASK                  (0xF0000000)
411 +#define MPI_SAS_PHY_PGAD_FORM_SHIFT                 (28)
412 +#define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER            (0x0)
413 +#define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX         (0x1)
414 +#define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK            (0x000000FF)
415 +#define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT           (0)
416 +#define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK         (0x0000FFFF)
417 +#define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT        (0)
418 +
419 +#define MPI_SAS_ENCLOS_PGAD_FORM_MASK               (0xF0000000)
420 +#define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT              (28)
421 +#define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE    (0x00000000)
422 +#define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE             (0x00000001)
423 +#define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK         (0x0000FFFF)
424 +#define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT        (0)
425 +#define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK           (0x0000FFFF)
426 +#define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT          (0)
427 +
428 +
429 +
430 +/****************************************************************************
431 +*   Config Request Message
432 +****************************************************************************/
433 +typedef struct _MSG_CONFIG
434 +{
435 +    U8                      Action;                     /* 00h */
436 +    U8                      Reserved;                   /* 01h */
437 +    U8                      ChainOffset;                /* 02h */
438 +    U8                      Function;                   /* 03h */
439 +    U16                     ExtPageLength;              /* 04h */
440 +    U8                      ExtPageType;                /* 06h */
441 +    U8                      MsgFlags;                   /* 07h */
442 +    U32                     MsgContext;                 /* 08h */
443 +    U8                      Reserved2[8];               /* 0Ch */
444 +    CONFIG_PAGE_HEADER      Header;                     /* 14h */
445 +    U32                     PageAddress;                /* 18h */
446 +    SGE_IO_UNION            PageBufferSGE;              /* 1Ch */
447 +} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
448 +  Config_t, MPI_POINTER pConfig_t;
449 +
450 +
451 +/****************************************************************************
452 +*   Action field values
453 +****************************************************************************/
454 +#define MPI_CONFIG_ACTION_PAGE_HEADER               (0x00)
455 +#define MPI_CONFIG_ACTION_PAGE_READ_CURRENT         (0x01)
456 +#define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT        (0x02)
457 +#define MPI_CONFIG_ACTION_PAGE_DEFAULT              (0x03)
458 +#define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM          (0x04)
459 +#define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT         (0x05)
460 +#define MPI_CONFIG_ACTION_PAGE_READ_NVRAM           (0x06)
461 +
462 +
463 +/* Config Reply Message */
464 +typedef struct _MSG_CONFIG_REPLY
465 +{
466 +    U8                      Action;                     /* 00h */
467 +    U8                      Reserved;                   /* 01h */
468 +    U8                      MsgLength;                  /* 02h */
469 +    U8                      Function;                   /* 03h */
470 +    U16                     ExtPageLength;              /* 04h */
471 +    U8                      ExtPageType;                /* 06h */
472 +    U8                      MsgFlags;                   /* 07h */
473 +    U32                     MsgContext;                 /* 08h */
474 +    U8                      Reserved2[2];               /* 0Ch */
475 +    U16                     IOCStatus;                  /* 0Eh */
476 +    U32                     IOCLogInfo;                 /* 10h */
477 +    CONFIG_PAGE_HEADER      Header;                     /* 14h */
478 +} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
479 +  ConfigReply_t, MPI_POINTER pConfigReply_t;
480 +
481 +
482 +
483 +/*****************************************************************************
484 +*
485 +*               C o n f i g u r a t i o n    P a g e s
486 +*
487 +*****************************************************************************/
488 +
489 +/****************************************************************************
490 +*   Manufacturing Config pages
491 +****************************************************************************/
492 +#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC          (0x1000)
493 +/* Fibre Channel */
494 +#define MPI_MANUFACTPAGE_DEVICEID_FC909             (0x0621)
495 +#define MPI_MANUFACTPAGE_DEVICEID_FC919             (0x0624)
496 +#define MPI_MANUFACTPAGE_DEVICEID_FC929             (0x0622)
497 +#define MPI_MANUFACTPAGE_DEVICEID_FC919X            (0x0628)
498 +#define MPI_MANUFACTPAGE_DEVICEID_FC929X            (0x0626)
499 +#define MPI_MANUFACTPAGE_DEVICEID_FC939X            (0x0642)
500 +#define MPI_MANUFACTPAGE_DEVICEID_FC949X            (0x0640)
501 +#define MPI_MANUFACTPAGE_DEVICEID_FC949ES           (0x0646)
502 +/* SCSI */
503 +#define MPI_MANUFACTPAGE_DEVID_53C1030              (0x0030)
504 +#define MPI_MANUFACTPAGE_DEVID_53C1030ZC            (0x0031)
505 +#define MPI_MANUFACTPAGE_DEVID_1030_53C1035         (0x0032)
506 +#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035       (0x0033)
507 +#define MPI_MANUFACTPAGE_DEVID_53C1035              (0x0040)
508 +#define MPI_MANUFACTPAGE_DEVID_53C1035ZC            (0x0041)
509 +/* SAS */
510 +#define MPI_MANUFACTPAGE_DEVID_SAS1064              (0x0050)
511 +#define MPI_MANUFACTPAGE_DEVID_SAS1064A             (0x005C)
512 +#define MPI_MANUFACTPAGE_DEVID_SAS1064E             (0x0056)
513 +#define MPI_MANUFACTPAGE_DEVID_SAS1066              (0x005E)
514 +#define MPI_MANUFACTPAGE_DEVID_SAS1066E             (0x005A)
515 +#define MPI_MANUFACTPAGE_DEVID_SAS1068              (0x0054)
516 +#define MPI_MANUFACTPAGE_DEVID_SAS1068E             (0x0058)
517 +#define MPI_MANUFACTPAGE_DEVID_SAS1078              (0x0060)
518 +
519 +
520 +typedef struct _CONFIG_PAGE_MANUFACTURING_0
521 +{
522 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
523 +    U8                      ChipName[16];               /* 04h */
524 +    U8                      ChipRevision[8];            /* 14h */
525 +    U8                      BoardName[16];              /* 1Ch */
526 +    U8                      BoardAssembly[16];          /* 2Ch */
527 +    U8                      BoardTracerNumber[16];      /* 3Ch */
528 +
529 +} CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
530 +  ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
531 +
532 +#define MPI_MANUFACTURING0_PAGEVERSION                 (0x00)
533 +
534 +
535 +typedef struct _CONFIG_PAGE_MANUFACTURING_1
536 +{
537 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
538 +    U8                      VPD[256];                   /* 04h */
539 +} CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
540 +  ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
541 +
542 +#define MPI_MANUFACTURING1_PAGEVERSION                 (0x00)
543 +
544 +
545 +typedef struct _MPI_CHIP_REVISION_ID
546 +{
547 +    U16 DeviceID;                                       /* 00h */
548 +    U8  PCIRevisionID;                                  /* 02h */
549 +    U8  Reserved;                                       /* 03h */
550 +} MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
551 +  MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
552 +
553 +
554 +/*
555 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
556 + * one and check Header.PageLength at runtime.
557 + */
558 +#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
559 +#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS    (1)
560 +#endif
561 +
562 +typedef struct _CONFIG_PAGE_MANUFACTURING_2
563 +{
564 +    CONFIG_PAGE_HEADER      Header;                                 /* 00h */
565 +    MPI_CHIP_REVISION_ID    ChipId;                                 /* 04h */
566 +    U32                     HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
567 +} CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
568 +  ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
569 +
570 +#define MPI_MANUFACTURING2_PAGEVERSION                  (0x00)
571 +
572 +
573 +/*
574 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
575 + * one and check Header.PageLength at runtime.
576 + */
577 +#ifndef MPI_MAN_PAGE_3_INFO_WORDS
578 +#define MPI_MAN_PAGE_3_INFO_WORDS           (1)
579 +#endif
580 +
581 +typedef struct _CONFIG_PAGE_MANUFACTURING_3
582 +{
583 +    CONFIG_PAGE_HEADER                  Header;                     /* 00h */
584 +    MPI_CHIP_REVISION_ID                ChipId;                     /* 04h */
585 +    U32                                 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
586 +} CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
587 +  ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
588 +
589 +#define MPI_MANUFACTURING3_PAGEVERSION                  (0x00)
590 +
591 +
592 +typedef struct _CONFIG_PAGE_MANUFACTURING_4
593 +{
594 +    CONFIG_PAGE_HEADER              Header;             /* 00h */
595 +    U32                             Reserved1;          /* 04h */
596 +    U8                              InfoOffset0;        /* 08h */
597 +    U8                              InfoSize0;          /* 09h */
598 +    U8                              InfoOffset1;        /* 0Ah */
599 +    U8                              InfoSize1;          /* 0Bh */
600 +    U8                              InquirySize;        /* 0Ch */
601 +    U8                              Flags;              /* 0Dh */
602 +    U16                             Reserved2;          /* 0Eh */
603 +    U8                              InquiryData[56];    /* 10h */
604 +    U32                             ISVolumeSettings;   /* 48h */
605 +    U32                             IMEVolumeSettings;  /* 4Ch */
606 +    U32                             IMVolumeSettings;   /* 50h */
607 +    U32                             Reserved3;          /* 54h */
608 +    U32                             Reserved4;          /* 58h */
609 +    U8                              ISDataScrubRate;    /* 5Ch */
610 +    U8                              ISResyncRate;       /* 5Dh */
611 +    U16                             Reserved5;          /* 5Eh */
612 +    U8                              IMEDataScrubRate;   /* 60h */
613 +    U8                              IMEResyncRate;      /* 61h */
614 +    U16                             Reserved6;          /* 62h */
615 +    U8                              IMDataScrubRate;    /* 64h */
616 +    U8                              IMResyncRate;       /* 65h */
617 +    U16                             Reserved7;          /* 66h */
618 +    U32                             Reserved8;          /* 68h */
619 +    U32                             Reserved9;          /* 6Ch */
620 +} CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
621 +  ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
622 +
623 +#define MPI_MANUFACTURING4_PAGEVERSION                  (0x02)
624 +
625 +/* defines for the Flags field */
626 +#define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA                 (0x01)
627 +
628 +
629 +typedef struct _CONFIG_PAGE_MANUFACTURING_5
630 +{
631 +    CONFIG_PAGE_HEADER              Header;             /* 00h */
632 +    U64                             BaseWWID;           /* 04h */
633 +    U8                              Flags;              /* 0Ch */
634 +    U8                              Reserved1;          /* 0Dh */
635 +    U16                             Reserved2;          /* 0Eh */
636 +} CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
637 +  ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
638 +
639 +#define MPI_MANUFACTURING5_PAGEVERSION                  (0x01)
640 +
641 +/* defines for the Flags field */
642 +#define MPI_MANPAGE5_TWO_WWID_PER_PHY                   (0x01)
643 +
644 +
645 +typedef struct _CONFIG_PAGE_MANUFACTURING_6
646 +{
647 +    CONFIG_PAGE_HEADER              Header;             /* 00h */
648 +    U32                             ProductSpecificInfo;/* 04h */
649 +} CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
650 +  ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
651 +
652 +#define MPI_MANUFACTURING6_PAGEVERSION                  (0x00)
653 +
654 +
655 +/****************************************************************************
656 +*   IO Unit Config Pages
657 +****************************************************************************/
658 +
659 +typedef struct _CONFIG_PAGE_IO_UNIT_0
660 +{
661 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
662 +    U64                     UniqueValue;                /* 04h */
663 +} CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
664 +  IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
665 +
666 +#define MPI_IOUNITPAGE0_PAGEVERSION                     (0x00)
667 +
668 +
669 +typedef struct _CONFIG_PAGE_IO_UNIT_1
670 +{
671 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
672 +    U32                     Flags;                      /* 04h */
673 +} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
674 +  IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
675 +
676 +#define MPI_IOUNITPAGE1_PAGEVERSION                     (0x01)
677 +
678 +/* IO Unit Page 1 Flags defines */
679 +#define MPI_IOUNITPAGE1_MULTI_FUNCTION                  (0x00000000)
680 +#define MPI_IOUNITPAGE1_SINGLE_FUNCTION                 (0x00000001)
681 +#define MPI_IOUNITPAGE1_MULTI_PATHING                   (0x00000002)
682 +#define MPI_IOUNITPAGE1_SINGLE_PATHING                  (0x00000000)
683 +#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID         (0x00000004)
684 +#define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING     (0x00000020)
685 +#define MPI_IOUNITPAGE1_DISABLE_IR                      (0x00000040)
686 +#define MPI_IOUNITPAGE1_FORCE_32                        (0x00000080)
687 +#define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE        (0x00000100)
688 +
689 +
690 +typedef struct _MPI_ADAPTER_INFO
691 +{
692 +    U8      PciBusNumber;                               /* 00h */
693 +    U8      PciDeviceAndFunctionNumber;                 /* 01h */
694 +    U16     AdapterFlags;                               /* 02h */
695 +} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
696 +  MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
697 +
698 +#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED                 (0x0001)
699 +#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS              (0x0002)
700 +
701 +typedef struct _CONFIG_PAGE_IO_UNIT_2
702 +{
703 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
704 +    U32                     Flags;                      /* 04h */
705 +    U32                     BiosVersion;                /* 08h */
706 +    MPI_ADAPTER_INFO        AdapterOrder[4];            /* 0Ch */
707 +    U32                     Reserved1;                  /* 1Ch */
708 +} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
709 +  IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
710 +
711 +#define MPI_IOUNITPAGE2_PAGEVERSION                     (0x02)
712 +
713 +#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR            (0x00000002)
714 +#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE            (0x00000004)
715 +#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE       (0x00000008)
716 +#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40          (0x00000010)
717 +
718 +#define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK     (0x000000E0)
719 +#define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY     (0x00000000)
720 +#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY           (0x00000020)
721 +#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY       (0x00000040)
722 +
723 +
724 +/*
725 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
726 + * one and check Header.PageLength at runtime.
727 + */
728 +#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
729 +#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX     (1)
730 +#endif
731 +
732 +typedef struct _CONFIG_PAGE_IO_UNIT_3
733 +{
734 +    CONFIG_PAGE_HEADER      Header;                                   /* 00h */
735 +    U8                      GPIOCount;                                /* 04h */
736 +    U8                      Reserved1;                                /* 05h */
737 +    U16                     Reserved2;                                /* 06h */
738 +    U16                     GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
739 +} CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
740 +  IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
741 +
742 +#define MPI_IOUNITPAGE3_PAGEVERSION                     (0x01)
743 +
744 +#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK              (0xFC)
745 +#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT             (2)
746 +#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF                (0x00)
747 +#define MPI_IOUNITPAGE3_GPIO_SETTING_ON                 (0x01)
748 +
749 +
750 +typedef struct _CONFIG_PAGE_IO_UNIT_4
751 +{
752 +    CONFIG_PAGE_HEADER      Header;                                   /* 00h */
753 +    U32                     Reserved1;                                /* 04h */
754 +    SGE_SIMPLE_UNION        FWImageSGE;                               /* 08h */
755 +} CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
756 +  IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
757 +
758 +#define MPI_IOUNITPAGE4_PAGEVERSION                     (0x00)
759 +
760 +
761 +/****************************************************************************
762 +*   IOC Config Pages
763 +****************************************************************************/
764 +
765 +typedef struct _CONFIG_PAGE_IOC_0
766 +{
767 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
768 +    U32                     TotalNVStore;               /* 04h */
769 +    U32                     FreeNVStore;                /* 08h */
770 +    U16                     VendorID;                   /* 0Ch */
771 +    U16                     DeviceID;                   /* 0Eh */
772 +    U8                      RevisionID;                 /* 10h */
773 +    U8                      Reserved[3];                /* 11h */
774 +    U32                     ClassCode;                  /* 14h */
775 +    U16                     SubsystemVendorID;          /* 18h */
776 +    U16                     SubsystemID;                /* 1Ah */
777 +} CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
778 +  IOCPage0_t, MPI_POINTER pIOCPage0_t;
779 +
780 +#define MPI_IOCPAGE0_PAGEVERSION                        (0x01)
781 +
782 +
783 +typedef struct _CONFIG_PAGE_IOC_1
784 +{
785 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
786 +    U32                     Flags;                      /* 04h */
787 +    U32                     CoalescingTimeout;          /* 08h */
788 +    U8                      CoalescingDepth;            /* 0Ch */
789 +    U8                      PCISlotNum;                 /* 0Dh */
790 +    U8                      Reserved[2];                /* 0Eh */
791 +} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
792 +  IOCPage1_t, MPI_POINTER pIOCPage1_t;
793 +
794 +#define MPI_IOCPAGE1_PAGEVERSION                        (0x03)
795 +
796 +/* defines for the Flags field */
797 +#define MPI_IOCPAGE1_EEDP_MODE_MASK                     (0x07000000)
798 +#define MPI_IOCPAGE1_EEDP_MODE_OFF                      (0x00000000)
799 +#define MPI_IOCPAGE1_EEDP_MODE_T10                      (0x01000000)
800 +#define MPI_IOCPAGE1_EEDP_MODE_LSI_1                    (0x02000000)
801 +#define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE    (0x00000010)
802 +#define MPI_IOCPAGE1_REPLY_COALESCING                   (0x00000001)
803 +
804 +#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN                 (0xFF)
805 +
806 +
807 +typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
808 +{
809 +    U8                          VolumeID;               /* 00h */
810 +    U8                          VolumeBus;              /* 01h */
811 +    U8                          VolumeIOC;              /* 02h */
812 +    U8                          VolumePageNumber;       /* 03h */
813 +    U8                          VolumeType;             /* 04h */
814 +    U8                          Flags;                  /* 05h */
815 +    U16                         Reserved3;              /* 06h */
816 +} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
817 +  ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
818 +
819 +/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
820 +
821 +#define MPI_RAID_VOL_TYPE_IS                        (0x00)
822 +#define MPI_RAID_VOL_TYPE_IME                       (0x01)
823 +#define MPI_RAID_VOL_TYPE_IM                        (0x02)
824 +#define MPI_RAID_VOL_TYPE_RAID_5                    (0x03)
825 +#define MPI_RAID_VOL_TYPE_RAID_6                    (0x04)
826 +#define MPI_RAID_VOL_TYPE_RAID_10                   (0x05)
827 +#define MPI_RAID_VOL_TYPE_RAID_50                   (0x06)
828 +#define MPI_RAID_VOL_TYPE_UNKNOWN                   (0xFF)
829 +
830 +/* IOC Page 2 Volume Flags values */
831 +
832 +#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE           (0x08)
833 +
834 +/*
835 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
836 + * one and check Header.PageLength at runtime.
837 + */
838 +#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
839 +#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX      (1)
840 +#endif
841 +
842 +typedef struct _CONFIG_PAGE_IOC_2
843 +{
844 +    CONFIG_PAGE_HEADER          Header;                              /* 00h */
845 +    U32                         CapabilitiesFlags;                   /* 04h */
846 +    U8                          NumActiveVolumes;                    /* 08h */
847 +    U8                          MaxVolumes;                          /* 09h */
848 +    U8                          NumActivePhysDisks;                  /* 0Ah */
849 +    U8                          MaxPhysDisks;                        /* 0Bh */
850 +    CONFIG_PAGE_IOC_2_RAID_VOL  RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
851 +} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
852 +  IOCPage2_t, MPI_POINTER pIOCPage2_t;
853 +
854 +#define MPI_IOCPAGE2_PAGEVERSION                        (0x03)
855 +
856 +/* IOC Page 2 Capabilities flags */
857 +
858 +#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT               (0x00000001)
859 +#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT              (0x00000002)
860 +#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT               (0x00000004)
861 +#define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT           (0x00000008)
862 +#define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT           (0x00000010)
863 +#define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT          (0x00000020)
864 +#define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT          (0x00000040)
865 +#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT              (0x20000000)
866 +#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT            (0x40000000)
867 +#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT    (0x80000000)
868 +
869 +
870 +typedef struct _IOC_3_PHYS_DISK
871 +{
872 +    U8                          PhysDiskID;             /* 00h */
873 +    U8                          PhysDiskBus;            /* 01h */
874 +    U8                          PhysDiskIOC;            /* 02h */
875 +    U8                          PhysDiskNum;            /* 03h */
876 +} IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
877 +  Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
878 +
879 +/*
880 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
881 + * one and check Header.PageLength at runtime.
882 + */
883 +#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
884 +#define MPI_IOC_PAGE_3_PHYSDISK_MAX         (1)
885 +#endif
886 +
887 +typedef struct _CONFIG_PAGE_IOC_3
888 +{
889 +    CONFIG_PAGE_HEADER          Header;                                /* 00h */
890 +    U8                          NumPhysDisks;                          /* 04h */
891 +    U8                          Reserved1;                             /* 05h */
892 +    U16                         Reserved2;                             /* 06h */
893 +    IOC_3_PHYS_DISK             PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
894 +} CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
895 +  IOCPage3_t, MPI_POINTER pIOCPage3_t;
896 +
897 +#define MPI_IOCPAGE3_PAGEVERSION                        (0x00)
898 +
899 +
900 +typedef struct _IOC_4_SEP
901 +{
902 +    U8                          SEPTargetID;            /* 00h */
903 +    U8                          SEPBus;                 /* 01h */
904 +    U16                         Reserved;               /* 02h */
905 +} IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
906 +  Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
907 +
908 +/*
909 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
910 + * one and check Header.PageLength at runtime.
911 + */
912 +#ifndef MPI_IOC_PAGE_4_SEP_MAX
913 +#define MPI_IOC_PAGE_4_SEP_MAX              (1)
914 +#endif
915 +
916 +typedef struct _CONFIG_PAGE_IOC_4
917 +{
918 +    CONFIG_PAGE_HEADER          Header;                         /* 00h */
919 +    U8                          ActiveSEP;                      /* 04h */
920 +    U8                          MaxSEP;                         /* 05h */
921 +    U16                         Reserved1;                      /* 06h */
922 +    IOC_4_SEP                   SEP[MPI_IOC_PAGE_4_SEP_MAX];    /* 08h */
923 +} CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
924 +  IOCPage4_t, MPI_POINTER pIOCPage4_t;
925 +
926 +#define MPI_IOCPAGE4_PAGEVERSION                        (0x00)
927 +
928 +
929 +typedef struct _IOC_5_HOT_SPARE
930 +{
931 +    U8                          PhysDiskNum;            /* 00h */
932 +    U8                          Reserved;               /* 01h */
933 +    U8                          HotSparePool;           /* 02h */
934 +    U8                          Flags;                   /* 03h */
935 +} IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
936 +  Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
937 +
938 +/* IOC Page 5 HotSpare Flags */
939 +#define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE                 (0x01)
940 +
941 +/*
942 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
943 + * one and check Header.PageLength at runtime.
944 + */
945 +#ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
946 +#define MPI_IOC_PAGE_5_HOT_SPARE_MAX        (1)
947 +#endif
948 +
949 +typedef struct _CONFIG_PAGE_IOC_5
950 +{
951 +    CONFIG_PAGE_HEADER          Header;                         /* 00h */
952 +    U32                         Reserved1;                      /* 04h */
953 +    U8                          NumHotSpares;                   /* 08h */
954 +    U8                          Reserved2;                      /* 09h */
955 +    U16                         Reserved3;                      /* 0Ah */
956 +    IOC_5_HOT_SPARE             HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
957 +} CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
958 +  IOCPage5_t, MPI_POINTER pIOCPage5_t;
959 +
960 +#define MPI_IOCPAGE5_PAGEVERSION                        (0x00)
961 +
962 +
963 +/****************************************************************************
964 +*   BIOS Config Pages
965 +****************************************************************************/
966 +
967 +typedef struct _CONFIG_PAGE_BIOS_1
968 +{
969 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
970 +    U32                     BiosOptions;                /* 04h */
971 +    U32                     IOCSettings;                /* 08h */
972 +    U32                     Reserved1;                  /* 0Ch */
973 +    U32                     DeviceSettings;             /* 10h */
974 +    U16                     NumberOfDevices;            /* 14h */
975 +    U16                     Reserved2;                  /* 16h */
976 +    U16                     IOTimeoutBlockDevicesNonRM; /* 18h */
977 +    U16                     IOTimeoutSequential;        /* 1Ah */
978 +    U16                     IOTimeoutOther;             /* 1Ch */
979 +    U16                     IOTimeoutBlockDevicesRM;    /* 1Eh */
980 +} CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
981 +  BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
982 +
983 +#define MPI_BIOSPAGE1_PAGEVERSION                       (0x02)
984 +
985 +/* values for the BiosOptions field */
986 +#define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE                (0x00000400)
987 +#define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE                 (0x00000200)
988 +#define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE                (0x00000100)
989 +#define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS              (0x00000001)
990 +
991 +/* values for the IOCSettings field */
992 +#define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY     (0x00F00000)
993 +#define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY    (20)
994 +#define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE       (0x00030000)
995 +#define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT        (0x00000000)
996 +#define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT           (0x00010000)
997 +
998 +#define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP    (0x0000F000)
999 +#define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP   (12)
1000 +
1001 +#define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY          (0x00000F00)
1002 +#define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY         (8)
1003 +
1004 +#define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING            (0x000000C0)
1005 +#define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING            (0x00000000)
1006 +#define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING            (0x00000040)
1007 +#define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING           (0x00000080)
1008 +
1009 +#define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT       (0x00000030)
1010 +#define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT                 (0x00000000)
1011 +#define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT               (0x00000010)
1012 +#define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT                 (0x00000020)
1013 +#define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT                (0x00000030)
1014 +
1015 +#define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS              (0x00000008)
1016 +
1017 +/* values for the DeviceSettings field */
1018 +#define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN            (0x00000008)
1019 +#define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN             (0x00000004)
1020 +#define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN         (0x00000002)
1021 +#define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN          (0x00000001)
1022 +
1023 +typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1024 +{
1025 +    U32         Reserved1;                              /* 00h */
1026 +    U32         Reserved2;                              /* 04h */
1027 +    U32         Reserved3;                              /* 08h */
1028 +    U32         Reserved4;                              /* 0Ch */
1029 +    U32         Reserved5;                              /* 10h */
1030 +    U32         Reserved6;                              /* 14h */
1031 +    U32         Reserved7;                              /* 18h */
1032 +    U32         Reserved8;                              /* 1Ch */
1033 +    U32         Reserved9;                              /* 20h */
1034 +    U32         Reserved10;                             /* 24h */
1035 +    U32         Reserved11;                             /* 28h */
1036 +    U32         Reserved12;                             /* 2Ch */
1037 +    U32         Reserved13;                             /* 30h */
1038 +    U32         Reserved14;                             /* 34h */
1039 +    U32         Reserved15;                             /* 38h */
1040 +    U32         Reserved16;                             /* 3Ch */
1041 +    U32         Reserved17;                             /* 40h */
1042 +} MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1043 +
1044 +typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1045 +{
1046 +    U8          TargetID;                               /* 00h */
1047 +    U8          Bus;                                    /* 01h */
1048 +    U8          AdapterNumber;                          /* 02h */
1049 +    U8          Reserved1;                              /* 03h */
1050 +    U32         Reserved2;                              /* 04h */
1051 +    U32         Reserved3;                              /* 08h */
1052 +    U32         Reserved4;                              /* 0Ch */
1053 +    U8          LUN[8];                                 /* 10h */
1054 +    U32         Reserved5;                              /* 18h */
1055 +    U32         Reserved6;                              /* 1Ch */
1056 +    U32         Reserved7;                              /* 20h */
1057 +    U32         Reserved8;                              /* 24h */
1058 +    U32         Reserved9;                              /* 28h */
1059 +    U32         Reserved10;                             /* 2Ch */
1060 +    U32         Reserved11;                             /* 30h */
1061 +    U32         Reserved12;                             /* 34h */
1062 +    U32         Reserved13;                             /* 38h */
1063 +    U32         Reserved14;                             /* 3Ch */
1064 +    U32         Reserved15;                             /* 40h */
1065 +} MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1066 +
1067 +typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1068 +{
1069 +    U8          TargetID;                               /* 00h */
1070 +    U8          Bus;                                    /* 01h */
1071 +    U16         PCIAddress;                             /* 02h */
1072 +    U32         Reserved1;                              /* 04h */
1073 +    U32         Reserved2;                              /* 08h */
1074 +    U32         Reserved3;                              /* 0Ch */
1075 +    U8          LUN[8];                                 /* 10h */
1076 +    U32         Reserved4;                              /* 18h */
1077 +    U32         Reserved5;                              /* 1Ch */
1078 +    U32         Reserved6;                              /* 20h */
1079 +    U32         Reserved7;                              /* 24h */
1080 +    U32         Reserved8;                              /* 28h */
1081 +    U32         Reserved9;                              /* 2Ch */
1082 +    U32         Reserved10;                             /* 30h */
1083 +    U32         Reserved11;                             /* 34h */
1084 +    U32         Reserved12;                             /* 38h */
1085 +    U32         Reserved13;                             /* 3Ch */
1086 +    U32         Reserved14;                             /* 40h */
1087 +} MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1088 +
1089 +typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1090 +{
1091 +    U8          TargetID;                               /* 00h */
1092 +    U8          Bus;                                    /* 01h */
1093 +    U8          PCISlotNumber;                          /* 02h */
1094 +    U8          Reserved1;                              /* 03h */
1095 +    U32         Reserved2;                              /* 04h */
1096 +    U32         Reserved3;                              /* 08h */
1097 +    U32         Reserved4;                              /* 0Ch */
1098 +    U8          LUN[8];                                 /* 10h */
1099 +    U32         Reserved5;                              /* 18h */
1100 +    U32         Reserved6;                              /* 1Ch */
1101 +    U32         Reserved7;                              /* 20h */
1102 +    U32         Reserved8;                              /* 24h */
1103 +    U32         Reserved9;                              /* 28h */
1104 +    U32         Reserved10;                             /* 2Ch */
1105 +    U32         Reserved11;                             /* 30h */
1106 +    U32         Reserved12;                             /* 34h */
1107 +    U32         Reserved13;                             /* 38h */
1108 +    U32         Reserved14;                             /* 3Ch */
1109 +    U32         Reserved15;                             /* 40h */
1110 +} MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1111 +
1112 +typedef struct _MPI_BOOT_DEVICE_FC_WWN
1113 +{
1114 +    U64         WWPN;                                   /* 00h */
1115 +    U32         Reserved1;                              /* 08h */
1116 +    U32         Reserved2;                              /* 0Ch */
1117 +    U8          LUN[8];                                 /* 10h */
1118 +    U32         Reserved3;                              /* 18h */
1119 +    U32         Reserved4;                              /* 1Ch */
1120 +    U32         Reserved5;                              /* 20h */
1121 +    U32         Reserved6;                              /* 24h */
1122 +    U32         Reserved7;                              /* 28h */
1123 +    U32         Reserved8;                              /* 2Ch */
1124 +    U32         Reserved9;                              /* 30h */
1125 +    U32         Reserved10;                             /* 34h */
1126 +    U32         Reserved11;                             /* 38h */
1127 +    U32         Reserved12;                             /* 3Ch */
1128 +    U32         Reserved13;                             /* 40h */
1129 +} MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1130 +
1131 +typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1132 +{
1133 +    U64         SASAddress;                             /* 00h */
1134 +    U32         Reserved1;                              /* 08h */
1135 +    U32         Reserved2;                              /* 0Ch */
1136 +    U8          LUN[8];                                 /* 10h */
1137 +    U32         Reserved3;                              /* 18h */
1138 +    U32         Reserved4;                              /* 1Ch */
1139 +    U32         Reserved5;                              /* 20h */
1140 +    U32         Reserved6;                              /* 24h */
1141 +    U32         Reserved7;                              /* 28h */
1142 +    U32         Reserved8;                              /* 2Ch */
1143 +    U32         Reserved9;                              /* 30h */
1144 +    U32         Reserved10;                             /* 34h */
1145 +    U32         Reserved11;                             /* 38h */
1146 +    U32         Reserved12;                             /* 3Ch */
1147 +    U32         Reserved13;                             /* 40h */
1148 +} MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1149 +
1150 +typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1151 +{
1152 +    U64         EnclosureLogicalID;                     /* 00h */
1153 +    U32         Reserved1;                              /* 08h */
1154 +    U32         Reserved2;                              /* 0Ch */
1155 +    U8          LUN[8];                                 /* 10h */
1156 +    U16         SlotNumber;                             /* 18h */
1157 +    U16         Reserved3;                              /* 1Ah */
1158 +    U32         Reserved4;                              /* 1Ch */
1159 +    U32         Reserved5;                              /* 20h */
1160 +    U32         Reserved6;                              /* 24h */
1161 +    U32         Reserved7;                              /* 28h */
1162 +    U32         Reserved8;                              /* 2Ch */
1163 +    U32         Reserved9;                              /* 30h */
1164 +    U32         Reserved10;                             /* 34h */
1165 +    U32         Reserved11;                             /* 38h */
1166 +    U32         Reserved12;                             /* 3Ch */
1167 +    U32         Reserved13;                             /* 40h */
1168 +} MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1169 +  MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1170 +
1171 +typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1172 +{
1173 +    MPI_BOOT_DEVICE_ADAPTER_ORDER   AdapterOrder;
1174 +    MPI_BOOT_DEVICE_ADAPTER_NUMBER  AdapterNumber;
1175 +    MPI_BOOT_DEVICE_PCI_ADDRESS     PCIAddress;
1176 +    MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1177 +    MPI_BOOT_DEVICE_FC_WWN          FcWwn;
1178 +    MPI_BOOT_DEVICE_SAS_WWN         SasWwn;
1179 +    MPI_BOOT_DEVICE_ENCLOSURE_SLOT  EnclosureSlot;
1180 +} MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1181 +
1182 +typedef struct _CONFIG_PAGE_BIOS_2
1183 +{
1184 +    CONFIG_PAGE_HEADER          Header;                 /* 00h */
1185 +    U32                         Reserved1;              /* 04h */
1186 +    U32                         Reserved2;              /* 08h */
1187 +    U32                         Reserved3;              /* 0Ch */
1188 +    U32                         Reserved4;              /* 10h */
1189 +    U32                         Reserved5;              /* 14h */
1190 +    U32                         Reserved6;              /* 18h */
1191 +    U8                          BootDeviceForm;         /* 1Ch */
1192 +    U8                          Reserved7;              /* 1Dh */
1193 +    U16                         Reserved8;              /* 1Eh */
1194 +    MPI_BIOSPAGE2_BOOT_DEVICE   BootDevice;             /* 20h */
1195 +} CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1196 +  BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1197 +
1198 +#define MPI_BIOSPAGE2_PAGEVERSION                       (0x01)
1199 +
1200 +#define MPI_BIOSPAGE2_FORM_MASK                         (0x0F)
1201 +#define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER                (0x00)
1202 +#define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER               (0x01)
1203 +#define MPI_BIOSPAGE2_FORM_PCI_ADDRESS                  (0x02)
1204 +#define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER              (0x03)
1205 +#define MPI_BIOSPAGE2_FORM_FC_WWN                       (0x04)
1206 +#define MPI_BIOSPAGE2_FORM_SAS_WWN                      (0x05)
1207 +#define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT               (0x06)
1208 +
1209 +
1210 +/****************************************************************************
1211 +*   SCSI Port Config Pages
1212 +****************************************************************************/
1213 +
1214 +typedef struct _CONFIG_PAGE_SCSI_PORT_0
1215 +{
1216 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1217 +    U32                     Capabilities;               /* 04h */
1218 +    U32                     PhysicalInterface;          /* 08h */
1219 +} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1220 +  SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1221 +
1222 +#define MPI_SCSIPORTPAGE0_PAGEVERSION                   (0x02)
1223 +
1224 +#define MPI_SCSIPORTPAGE0_CAP_IU                        (0x00000001)
1225 +#define MPI_SCSIPORTPAGE0_CAP_DT                        (0x00000002)
1226 +#define MPI_SCSIPORTPAGE0_CAP_QAS                       (0x00000004)
1227 +#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK      (0x0000FF00)
1228 +#define MPI_SCSIPORTPAGE0_SYNC_ASYNC                    (0x00)
1229 +#define MPI_SCSIPORTPAGE0_SYNC_5                        (0x32)
1230 +#define MPI_SCSIPORTPAGE0_SYNC_10                       (0x19)
1231 +#define MPI_SCSIPORTPAGE0_SYNC_20                       (0x0C)
1232 +#define MPI_SCSIPORTPAGE0_SYNC_33_33                    (0x0B)
1233 +#define MPI_SCSIPORTPAGE0_SYNC_40                       (0x0A)
1234 +#define MPI_SCSIPORTPAGE0_SYNC_80                       (0x09)
1235 +#define MPI_SCSIPORTPAGE0_SYNC_160                      (0x08)
1236 +#define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN                  (0xFF)
1237 +
1238 +#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD     (8)
1239 +#define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap)      \
1240 +    (  ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MIN_SYNC_PERIOD) \
1241 +    >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD          \
1242 +    )
1243 +#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK      (0x00FF0000)
1244 +#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET     (16)
1245 +#define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap)      \
1246 +    (  ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MAX_SYNC_OFFSET) \
1247 +    >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET          \
1248 +    )
1249 +#define MPI_SCSIPORTPAGE0_CAP_IDP                       (0x08000000)
1250 +#define MPI_SCSIPORTPAGE0_CAP_WIDE                      (0x20000000)
1251 +#define MPI_SCSIPORTPAGE0_CAP_AIP                       (0x80000000)
1252 +
1253 +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK          (0x00000003)
1254 +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD                (0x01)
1255 +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE                 (0x02)
1256 +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD                (0x03)
1257 +#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID         (0xFF000000)
1258 +#define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID        (24)
1259 +#define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID     (0xFE)
1260 +#define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID      (0xFF)
1261 +
1262 +
1263 +typedef struct _CONFIG_PAGE_SCSI_PORT_1
1264 +{
1265 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1266 +    U32                     Configuration;              /* 04h */
1267 +    U32                     OnBusTimerValue;            /* 08h */
1268 +    U8                      TargetConfig;               /* 0Ch */
1269 +    U8                      Reserved1;                  /* 0Dh */
1270 +    U16                     IDConfig;                   /* 0Eh */
1271 +} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1272 +  SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1273 +
1274 +#define MPI_SCSIPORTPAGE1_PAGEVERSION                   (0x03)
1275 +
1276 +/* Configuration values */
1277 +#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK         (0x000000FF)
1278 +#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK     (0xFFFF0000)
1279 +#define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID    (16)
1280 +
1281 +/* TargetConfig values */
1282 +#define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY        (0x01)
1283 +#define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG        (0x02)
1284 +
1285 +
1286 +typedef struct _MPI_DEVICE_INFO
1287 +{
1288 +    U8      Timeout;                                    /* 00h */
1289 +    U8      SyncFactor;                                 /* 01h */
1290 +    U16     DeviceFlags;                                /* 02h */
1291 +} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1292 +  MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1293 +
1294 +typedef struct _CONFIG_PAGE_SCSI_PORT_2
1295 +{
1296 +    CONFIG_PAGE_HEADER  Header;                         /* 00h */
1297 +    U32                 PortFlags;                      /* 04h */
1298 +    U32                 PortSettings;                   /* 08h */
1299 +    MPI_DEVICE_INFO     DeviceSettings[16];             /* 0Ch */
1300 +} CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
1301 +  SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1302 +
1303 +#define MPI_SCSIPORTPAGE2_PAGEVERSION                       (0x02)
1304 +
1305 +/* PortFlags values */
1306 +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW       (0x00000001)
1307 +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET       (0x00000004)
1308 +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS          (0x00000008)
1309 +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE    (0x00000010)
1310 +
1311 +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK                (0x00000060)
1312 +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV                (0x00000000)
1313 +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY          (0x00000020)
1314 +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV                 (0x00000060)
1315 +
1316 +
1317 +/* PortSettings values */
1318 +#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK                 (0x0000000F)
1319 +#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA                (0x00000030)
1320 +#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA             (0x00000000)
1321 +#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA                (0x00000010)
1322 +#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA                  (0x00000020)
1323 +#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA             (0x00000030)
1324 +#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA              (0x000000C0)
1325 +#define MPI_SCSIPORTPAGE2_PORT_RM_NONE                      (0x00000000)
1326 +#define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY                 (0x00000040)
1327 +#define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA                (0x00000080)
1328 +#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK            (0x00000F00)
1329 +#define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY           (8)
1330 +#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS    (0x00003000)
1331 +#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS         (0x00000000)
1332 +#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS         (0x00001000)
1333 +#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS          (0x00003000)
1334 +
1335 +#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE          (0x0001)
1336 +#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE             (0x0002)
1337 +#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE            (0x0004)
1338 +#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE           (0x0008)
1339 +#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE               (0x0010)
1340 +#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE                (0x0020)
1341 +
1342 +
1343 +/****************************************************************************
1344 +*   SCSI Target Device Config Pages
1345 +****************************************************************************/
1346 +
1347 +typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1348 +{
1349 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1350 +    U32                     NegotiatedParameters;       /* 04h */
1351 +    U32                     Information;                /* 08h */
1352 +} CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1353 +  SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1354 +
1355 +#define MPI_SCSIDEVPAGE0_PAGEVERSION                    (0x04)
1356 +
1357 +#define MPI_SCSIDEVPAGE0_NP_IU                          (0x00000001)
1358 +#define MPI_SCSIDEVPAGE0_NP_DT                          (0x00000002)
1359 +#define MPI_SCSIDEVPAGE0_NP_QAS                         (0x00000004)
1360 +#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS                    (0x00000008)
1361 +#define MPI_SCSIDEVPAGE0_NP_WR_FLOW                     (0x00000010)
1362 +#define MPI_SCSIDEVPAGE0_NP_RD_STRM                     (0x00000020)
1363 +#define MPI_SCSIDEVPAGE0_NP_RTI                         (0x00000040)
1364 +#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN                    (0x00000080)
1365 +#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK        (0x0000FF00)
1366 +#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD           (8)
1367 +#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK        (0x00FF0000)
1368 +#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET           (16)
1369 +#define MPI_SCSIDEVPAGE0_NP_IDP                         (0x08000000)
1370 +#define MPI_SCSIDEVPAGE0_NP_WIDE                        (0x20000000)
1371 +#define MPI_SCSIDEVPAGE0_NP_AIP                         (0x80000000)
1372 +
1373 +#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED         (0x00000001)
1374 +#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED             (0x00000002)
1375 +#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED             (0x00000004)
1376 +#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED              (0x00000008)
1377 +
1378 +
1379 +typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1380 +{
1381 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1382 +    U32                     RequestedParameters;        /* 04h */
1383 +    U32                     Reserved;                   /* 08h */
1384 +    U32                     Configuration;              /* 0Ch */
1385 +} CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1386 +  SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1387 +
1388 +#define MPI_SCSIDEVPAGE1_PAGEVERSION                    (0x05)
1389 +
1390 +#define MPI_SCSIDEVPAGE1_RP_IU                          (0x00000001)
1391 +#define MPI_SCSIDEVPAGE1_RP_DT                          (0x00000002)
1392 +#define MPI_SCSIDEVPAGE1_RP_QAS                         (0x00000004)
1393 +#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS                    (0x00000008)
1394 +#define MPI_SCSIDEVPAGE1_RP_WR_FLOW                     (0x00000010)
1395 +#define MPI_SCSIDEVPAGE1_RP_RD_STRM                     (0x00000020)
1396 +#define MPI_SCSIDEVPAGE1_RP_RTI                         (0x00000040)
1397 +#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN                    (0x00000080)
1398 +#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK        (0x0000FF00)
1399 +#define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD       (8)
1400 +#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK        (0x00FF0000)
1401 +#define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET       (16)
1402 +#define MPI_SCSIDEVPAGE1_RP_IDP                         (0x08000000)
1403 +#define MPI_SCSIDEVPAGE1_RP_WIDE                        (0x20000000)
1404 +#define MPI_SCSIDEVPAGE1_RP_AIP                         (0x80000000)
1405 +
1406 +#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED           (0x00000002)
1407 +#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED           (0x00000004)
1408 +#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE    (0x00000008)
1409 +#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG             (0x00000010)
1410 +
1411 +
1412 +typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1413 +{
1414 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1415 +    U32                     DomainValidation;           /* 04h */
1416 +    U32                     ParityPipeSelect;           /* 08h */
1417 +    U32                     DataPipeSelect;             /* 0Ch */
1418 +} CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1419 +  SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1420 +
1421 +#define MPI_SCSIDEVPAGE2_PAGEVERSION                    (0x01)
1422 +
1423 +#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE                  (0x00000010)
1424 +#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE     (0x00000020)
1425 +#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL              (0x00000380)
1426 +#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL         (0x00001C00)
1427 +#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL       (0x0000E000)
1428 +#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST                    (0x10000000)
1429 +#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST                    (0x20000000)
1430 +#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT                    (0x40000000)
1431 +#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT                    (0x80000000)
1432 +
1433 +#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK                   (0x00000003)
1434 +
1435 +#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK       (0x00000003)
1436 +#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK       (0x0000000C)
1437 +#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK       (0x00000030)
1438 +#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK       (0x000000C0)
1439 +#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK       (0x00000300)
1440 +#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK       (0x00000C00)
1441 +#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK       (0x00003000)
1442 +#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK       (0x0000C000)
1443 +#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK       (0x00030000)
1444 +#define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK       (0x000C0000)
1445 +#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK      (0x00300000)
1446 +#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK      (0x00C00000)
1447 +#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK      (0x03000000)
1448 +#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK      (0x0C000000)
1449 +#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK      (0x30000000)
1450 +#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK      (0xC0000000)
1451 +
1452 +
1453 +typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1454 +{
1455 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1456 +    U16                     MsgRejectCount;             /* 04h */
1457 +    U16                     PhaseErrorCount;            /* 06h */
1458 +    U16                     ParityErrorCount;           /* 08h */
1459 +    U16                     Reserved;                   /* 0Ah */
1460 +} CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1461 +  SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1462 +
1463 +#define MPI_SCSIDEVPAGE3_PAGEVERSION                    (0x00)
1464 +
1465 +#define MPI_SCSIDEVPAGE3_MAX_COUNTER                    (0xFFFE)
1466 +#define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER            (0xFFFF)
1467 +
1468 +
1469 +/****************************************************************************
1470 +*   FC Port Config Pages
1471 +****************************************************************************/
1472 +
1473 +typedef struct _CONFIG_PAGE_FC_PORT_0
1474 +{
1475 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1476 +    U32                     Flags;                      /* 04h */
1477 +    U8                      MPIPortNumber;              /* 08h */
1478 +    U8                      LinkType;                   /* 09h */
1479 +    U8                      PortState;                  /* 0Ah */
1480 +    U8                      Reserved;                   /* 0Bh */
1481 +    U32                     PortIdentifier;             /* 0Ch */
1482 +    U64                     WWNN;                       /* 10h */
1483 +    U64                     WWPN;                       /* 18h */
1484 +    U32                     SupportedServiceClass;      /* 20h */
1485 +    U32                     SupportedSpeeds;            /* 24h */
1486 +    U32                     CurrentSpeed;               /* 28h */
1487 +    U32                     MaxFrameSize;               /* 2Ch */
1488 +    U64                     FabricWWNN;                 /* 30h */
1489 +    U64                     FabricWWPN;                 /* 38h */
1490 +    U32                     DiscoveredPortsCount;       /* 40h */
1491 +    U32                     MaxInitiators;              /* 44h */
1492 +    U8                      MaxAliasesSupported;        /* 48h */
1493 +    U8                      MaxHardAliasesSupported;    /* 49h */
1494 +    U8                      NumCurrentAliases;          /* 4Ah */
1495 +    U8                      Reserved1;                  /* 4Bh */
1496 +} CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1497 +  FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1498 +
1499 +#define MPI_FCPORTPAGE0_PAGEVERSION                     (0x02)
1500 +
1501 +#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK                 (0x0000000F)
1502 +#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT             (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1503 +#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG             (MPI_PORTFACTS_PROTOCOL_TARGET)
1504 +#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN                  (MPI_PORTFACTS_PROTOCOL_LAN)
1505 +#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR           (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1506 +
1507 +#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED      (0x00000010)
1508 +#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED       (0x00000020)
1509 +#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID          (0x00000040)
1510 +
1511 +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK          (0x00000F00)
1512 +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT            (0x00000000)
1513 +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT     (0x00000100)
1514 +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP       (0x00000200)
1515 +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT      (0x00000400)
1516 +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP        (0x00000800)
1517 +
1518 +#define MPI_FCPORTPAGE0_LTYPE_RESERVED                  (0x00)
1519 +#define MPI_FCPORTPAGE0_LTYPE_OTHER                     (0x01)
1520 +#define MPI_FCPORTPAGE0_LTYPE_UNKNOWN                   (0x02)
1521 +#define MPI_FCPORTPAGE0_LTYPE_COPPER                    (0x03)
1522 +#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300               (0x04)
1523 +#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500               (0x05)
1524 +#define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI            (0x06)
1525 +#define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI              (0x07)
1526 +#define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI            (0x08)
1527 +#define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI              (0x09)
1528 +#define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE           (0x0A)
1529 +#define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE          (0x0B)
1530 +#define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE          (0x0C)
1531 +#define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE            (0x0D)
1532 +#define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE            (0x0E)
1533 +#define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE            (0x0F)
1534 +
1535 +#define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN               (0x01)      /*(SNIA)HBA_PORTSTATE_UNKNOWN       1 Unknown */
1536 +#define MPI_FCPORTPAGE0_PORTSTATE_ONLINE                (0x02)      /*(SNIA)HBA_PORTSTATE_ONLINE        2 Operational */
1537 +#define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE               (0x03)      /*(SNIA)HBA_PORTSTATE_OFFLINE       3 User Offline */
1538 +#define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED              (0x04)      /*(SNIA)HBA_PORTSTATE_BYPASSED      4 Bypassed */
1539 +#define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST              (0x05)      /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS   5 In diagnostics mode */
1540 +#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN              (0x06)      /*(SNIA)HBA_PORTSTATE_LINKDOWN      6 Link Down */
1541 +#define MPI_FCPORTPAGE0_PORTSTATE_ERROR                 (0x07)      /*(SNIA)HBA_PORTSTATE_ERROR         7 Port Error */
1542 +#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK              (0x08)      /*(SNIA)HBA_PORTSTATE_LOOPBACK      8 Loopback */
1543 +
1544 +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1                 (0x00000001)
1545 +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2                 (0x00000002)
1546 +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3                 (0x00000004)
1547 +
1548 +#define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN            (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0   Unknown - transceiver incapable of reporting */
1549 +#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED             (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT   1   1 GBit/sec */
1550 +#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED             (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT   2   2 GBit/sec */
1551 +#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED            (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT  4  10 GBit/sec */
1552 +#define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED             (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT   8   4 GBit/sec */
1553 +
1554 +#define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN            MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1555 +#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT             MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1556 +#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT             MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1557 +#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT            MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1558 +#define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT             MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1559 +#define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED    (0x00008000)        /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1560 +
1561 +
1562 +typedef struct _CONFIG_PAGE_FC_PORT_1
1563 +{
1564 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1565 +    U32                     Flags;                      /* 04h */
1566 +    U64                     NoSEEPROMWWNN;              /* 08h */
1567 +    U64                     NoSEEPROMWWPN;              /* 10h */
1568 +    U8                      HardALPA;                   /* 18h */
1569 +    U8                      LinkConfig;                 /* 19h */
1570 +    U8                      TopologyConfig;             /* 1Ah */
1571 +    U8                      AltConnector;               /* 1Bh */
1572 +    U8                      NumRequestedAliases;        /* 1Ch */
1573 +    U8                      RR_TOV;                     /* 1Dh */
1574 +    U8                      InitiatorDeviceTimeout;     /* 1Eh */
1575 +    U8                      InitiatorIoPendTimeout;     /* 1Fh */
1576 +} CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1577 +  FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1578 +
1579 +#define MPI_FCPORTPAGE1_PAGEVERSION                     (0x06)
1580 +
1581 +#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN         (0x08000000)
1582 +#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY     (0x04000000)
1583 +#define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS  (0x02000000)
1584 +#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS     (0x01000000)
1585 +#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID          (0x00800000)
1586 +#define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE              (0x00400000)
1587 +#define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK        (0x00200000)
1588 +#define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE   (0x00000080)
1589 +#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS         (0x00000070)
1590 +#define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG         (0x00000008)
1591 +#define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO             (0x00000004)
1592 +#define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS           (0x00000002)
1593 +#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID               (0x00000001)
1594 +#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN               (0x00000000)
1595 +
1596 +#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK                 (0xF0000000)
1597 +#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT                (28)
1598 +#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT             ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1599 +#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG             ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1600 +#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN                  ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1601 +#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR           ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1602 +
1603 +#define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS         (0x00000000)
1604 +#define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS   (0x00000010)
1605 +#define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS        (0x00000030)
1606 +#define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS          (0x00000050)
1607 +
1608 +#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED              (0xFF)
1609 +
1610 +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK              (0x0F)
1611 +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG              (0x00)
1612 +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG              (0x01)
1613 +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG              (0x02)
1614 +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG             (0x03)
1615 +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO              (0x0F)
1616 +
1617 +#define MPI_FCPORTPAGE1_TOPOLOGY_MASK                   (0x0F)
1618 +#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT                 (0x01)
1619 +#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT                  (0x02)
1620 +#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO                   (0x0F)
1621 +
1622 +#define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN                (0x00)
1623 +
1624 +#define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK      (0x7F)
1625 +#define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16           (0x80)
1626 +
1627 +
1628 +typedef struct _CONFIG_PAGE_FC_PORT_2
1629 +{
1630 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1631 +    U8                      NumberActive;               /* 04h */
1632 +    U8                      ALPA[127];                  /* 05h */
1633 +} CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1634 +  FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1635 +
1636 +#define MPI_FCPORTPAGE2_PAGEVERSION                     (0x01)
1637 +
1638 +
1639 +typedef struct _WWN_FORMAT
1640 +{
1641 +    U64                     WWNN;                       /* 00h */
1642 +    U64                     WWPN;                       /* 08h */
1643 +} WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1644 +  WWNFormat, MPI_POINTER pWWNFormat;
1645 +
1646 +typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1647 +{
1648 +    WWN_FORMAT              WWN;
1649 +    U32                     Did;
1650 +} FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1651 +  PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1652 +
1653 +typedef struct _FC_PORT_PERSISTENT
1654 +{
1655 +    FC_PORT_PERSISTENT_PHYSICAL_ID  PhysicalIdentifier; /* 00h */
1656 +    U8                              TargetID;           /* 10h */
1657 +    U8                              Bus;                /* 11h */
1658 +    U16                             Flags;              /* 12h */
1659 +} FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1660 +  PersistentData_t, MPI_POINTER pPersistentData_t;
1661 +
1662 +#define MPI_PERSISTENT_FLAGS_SHIFT                      (16)
1663 +#define MPI_PERSISTENT_FLAGS_ENTRY_VALID                (0x0001)
1664 +#define MPI_PERSISTENT_FLAGS_SCAN_ID                    (0x0002)
1665 +#define MPI_PERSISTENT_FLAGS_SCAN_LUNS                  (0x0004)
1666 +#define MPI_PERSISTENT_FLAGS_BOOT_DEVICE                (0x0008)
1667 +#define MPI_PERSISTENT_FLAGS_BY_DID                     (0x0080)
1668 +
1669 +/*
1670 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1671 + * one and check Header.PageLength at runtime.
1672 + */
1673 +#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1674 +#define MPI_FC_PORT_PAGE_3_ENTRY_MAX        (1)
1675 +#endif
1676 +
1677 +typedef struct _CONFIG_PAGE_FC_PORT_3
1678 +{
1679 +    CONFIG_PAGE_HEADER      Header;                                 /* 00h */
1680 +    FC_PORT_PERSISTENT      Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX];    /* 04h */
1681 +} CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1682 +  FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1683 +
1684 +#define MPI_FCPORTPAGE3_PAGEVERSION                     (0x01)
1685 +
1686 +
1687 +typedef struct _CONFIG_PAGE_FC_PORT_4
1688 +{
1689 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1690 +    U32                     PortFlags;                  /* 04h */
1691 +    U32                     PortSettings;               /* 08h */
1692 +} CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1693 +  FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1694 +
1695 +#define MPI_FCPORTPAGE4_PAGEVERSION                     (0x00)
1696 +
1697 +#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS        (0x00000008)
1698 +
1699 +#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA              (0x00000030)
1700 +#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA           (0x00000000)
1701 +#define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA              (0x00000010)
1702 +#define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA                (0x00000020)
1703 +#define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA           (0x00000030)
1704 +#define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA            (0x000000C0)
1705 +#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK          (0x00000F00)
1706 +
1707 +
1708 +typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1709 +{
1710 +    U8      Flags;                                      /* 00h */
1711 +    U8      AliasAlpa;                                  /* 01h */
1712 +    U16     Reserved;                                   /* 02h */
1713 +    U64     AliasWWNN;                                  /* 04h */
1714 +    U64     AliasWWPN;                                  /* 0Ch */
1715 +} CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1716 +  MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1717 +  FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1718 +
1719 +typedef struct _CONFIG_PAGE_FC_PORT_5
1720 +{
1721 +    CONFIG_PAGE_HEADER                  Header;         /* 00h */
1722 +    CONFIG_PAGE_FC_PORT_5_ALIAS_INFO    AliasInfo;      /* 04h */
1723 +} CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1724 +  FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1725 +
1726 +#define MPI_FCPORTPAGE5_PAGEVERSION                     (0x02)
1727 +
1728 +#define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED             (0x01)
1729 +#define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA                 (0x02)
1730 +#define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN                 (0x04)
1731 +#define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN                 (0x08)
1732 +#define MPI_FCPORTPAGE5_FLAGS_DISABLE                   (0x10)
1733 +
1734 +typedef struct _CONFIG_PAGE_FC_PORT_6
1735 +{
1736 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1737 +    U32                     Reserved;                   /* 04h */
1738 +    U64                     TimeSinceReset;             /* 08h */
1739 +    U64                     TxFrames;                   /* 10h */
1740 +    U64                     RxFrames;                   /* 18h */
1741 +    U64                     TxWords;                    /* 20h */
1742 +    U64                     RxWords;                    /* 28h */
1743 +    U64                     LipCount;                   /* 30h */
1744 +    U64                     NosCount;                   /* 38h */
1745 +    U64                     ErrorFrames;                /* 40h */
1746 +    U64                     DumpedFrames;               /* 48h */
1747 +    U64                     LinkFailureCount;           /* 50h */
1748 +    U64                     LossOfSyncCount;            /* 58h */
1749 +    U64                     LossOfSignalCount;          /* 60h */
1750 +    U64                     PrimativeSeqErrCount;       /* 68h */
1751 +    U64                     InvalidTxWordCount;         /* 70h */
1752 +    U64                     InvalidCrcCount;            /* 78h */
1753 +    U64                     FcpInitiatorIoCount;        /* 80h */
1754 +} CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
1755 +  FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1756 +
1757 +#define MPI_FCPORTPAGE6_PAGEVERSION                     (0x00)
1758 +
1759 +
1760 +typedef struct _CONFIG_PAGE_FC_PORT_7
1761 +{
1762 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1763 +    U32                     Reserved;                   /* 04h */
1764 +    U8                      PortSymbolicName[256];      /* 08h */
1765 +} CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
1766 +  FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1767 +
1768 +#define MPI_FCPORTPAGE7_PAGEVERSION                     (0x00)
1769 +
1770 +
1771 +typedef struct _CONFIG_PAGE_FC_PORT_8
1772 +{
1773 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1774 +    U32                     BitVector[8];               /* 04h */
1775 +} CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
1776 +  FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1777 +
1778 +#define MPI_FCPORTPAGE8_PAGEVERSION                     (0x00)
1779 +
1780 +
1781 +typedef struct _CONFIG_PAGE_FC_PORT_9
1782 +{
1783 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1784 +    U32                     Reserved;                   /* 04h */
1785 +    U64                     GlobalWWPN;                 /* 08h */
1786 +    U64                     GlobalWWNN;                 /* 10h */
1787 +    U32                     UnitType;                   /* 18h */
1788 +    U32                     PhysicalPortNumber;         /* 1Ch */
1789 +    U32                     NumAttachedNodes;           /* 20h */
1790 +    U16                     IPVersion;                  /* 24h */
1791 +    U16                     UDPPortNumber;              /* 26h */
1792 +    U8                      IPAddress[16];              /* 28h */
1793 +    U16                     Reserved1;                  /* 38h */
1794 +    U16                     TopologyDiscoveryFlags;     /* 3Ah */
1795 +} CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
1796 +  FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
1797 +
1798 +#define MPI_FCPORTPAGE9_PAGEVERSION                     (0x00)
1799 +
1800 +
1801 +typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
1802 +{
1803 +    U8                      Id;                         /* 10h */
1804 +    U8                      ExtId;                      /* 11h */
1805 +    U8                      Connector;                  /* 12h */
1806 +    U8                      Transceiver[8];             /* 13h */
1807 +    U8                      Encoding;                   /* 1Bh */
1808 +    U8                      BitRate_100mbs;             /* 1Ch */
1809 +    U8                      Reserved1;                  /* 1Dh */
1810 +    U8                      Length9u_km;                /* 1Eh */
1811 +    U8                      Length9u_100m;              /* 1Fh */
1812 +    U8                      Length50u_10m;              /* 20h */
1813 +    U8                      Length62p5u_10m;            /* 21h */
1814 +    U8                      LengthCopper_m;             /* 22h */
1815 +    U8                      Reseverved2;                /* 22h */
1816 +    U8                      VendorName[16];             /* 24h */
1817 +    U8                      Reserved3;                  /* 34h */
1818 +    U8                      VendorOUI[3];               /* 35h */
1819 +    U8                      VendorPN[16];               /* 38h */
1820 +    U8                      VendorRev[4];               /* 48h */
1821 +    U16                     Wavelength;                 /* 4Ch */
1822 +    U8                      Reserved4;                  /* 4Eh */
1823 +    U8                      CC_BASE;                    /* 4Fh */
1824 +} CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1825 +  MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1826 +  FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
1827 +
1828 +#define MPI_FCPORT10_BASE_ID_UNKNOWN        (0x00)
1829 +#define MPI_FCPORT10_BASE_ID_GBIC           (0x01)
1830 +#define MPI_FCPORT10_BASE_ID_FIXED          (0x02)
1831 +#define MPI_FCPORT10_BASE_ID_SFP            (0x03)
1832 +#define MPI_FCPORT10_BASE_ID_SFP_MIN        (0x04)
1833 +#define MPI_FCPORT10_BASE_ID_SFP_MAX        (0x7F)
1834 +#define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
1835 +
1836 +#define MPI_FCPORT10_BASE_EXTID_UNKNOWN     (0x00)
1837 +#define MPI_FCPORT10_BASE_EXTID_MODDEF1     (0x01)
1838 +#define MPI_FCPORT10_BASE_EXTID_MODDEF2     (0x02)
1839 +#define MPI_FCPORT10_BASE_EXTID_MODDEF3     (0x03)
1840 +#define MPI_FCPORT10_BASE_EXTID_SEEPROM     (0x04)
1841 +#define MPI_FCPORT10_BASE_EXTID_MODDEF5     (0x05)
1842 +#define MPI_FCPORT10_BASE_EXTID_MODDEF6     (0x06)
1843 +#define MPI_FCPORT10_BASE_EXTID_MODDEF7     (0x07)
1844 +#define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
1845 +
1846 +#define MPI_FCPORT10_BASE_CONN_UNKNOWN      (0x00)
1847 +#define MPI_FCPORT10_BASE_CONN_SC           (0x01)
1848 +#define MPI_FCPORT10_BASE_CONN_COPPER1      (0x02)
1849 +#define MPI_FCPORT10_BASE_CONN_COPPER2      (0x03)
1850 +#define MPI_FCPORT10_BASE_CONN_BNC_TNC      (0x04)
1851 +#define MPI_FCPORT10_BASE_CONN_COAXIAL      (0x05)
1852 +#define MPI_FCPORT10_BASE_CONN_FIBERJACK    (0x06)
1853 +#define MPI_FCPORT10_BASE_CONN_LC           (0x07)
1854 +#define MPI_FCPORT10_BASE_CONN_MT_RJ        (0x08)
1855 +#define MPI_FCPORT10_BASE_CONN_MU           (0x09)
1856 +#define MPI_FCPORT10_BASE_CONN_SG           (0x0A)
1857 +#define MPI_FCPORT10_BASE_CONN_OPT_PIGT     (0x0B)
1858 +#define MPI_FCPORT10_BASE_CONN_RSV1_MIN     (0x0C)
1859 +#define MPI_FCPORT10_BASE_CONN_RSV1_MAX     (0x1F)
1860 +#define MPI_FCPORT10_BASE_CONN_HSSDC_II     (0x20)
1861 +#define MPI_FCPORT10_BASE_CONN_CPR_PIGT     (0x21)
1862 +#define MPI_FCPORT10_BASE_CONN_RSV2_MIN     (0x22)
1863 +#define MPI_FCPORT10_BASE_CONN_RSV2_MAX     (0x7F)
1864 +#define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK  (0x80)
1865 +
1866 +#define MPI_FCPORT10_BASE_ENCODE_UNSPEC     (0x00)
1867 +#define MPI_FCPORT10_BASE_ENCODE_8B10B      (0x01)
1868 +#define MPI_FCPORT10_BASE_ENCODE_4B5B       (0x02)
1869 +#define MPI_FCPORT10_BASE_ENCODE_NRZ        (0x03)
1870 +#define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
1871 +
1872 +
1873 +typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
1874 +{
1875 +    U8                      Options[2];                 /* 50h */
1876 +    U8                      BitRateMax;                 /* 52h */
1877 +    U8                      BitRateMin;                 /* 53h */
1878 +    U8                      VendorSN[16];               /* 54h */
1879 +    U8                      DateCode[8];                /* 64h */
1880 +    U8                      DiagMonitoringType;         /* 6Ch */
1881 +    U8                      EnhancedOptions;            /* 6Dh */
1882 +    U8                      SFF8472Compliance;          /* 6Eh */
1883 +    U8                      CC_EXT;                     /* 6Fh */
1884 +} CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1885 +  MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1886 +  FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
1887 +
1888 +#define MPI_FCPORT10_EXT_OPTION1_RATESEL    (0x20)
1889 +#define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
1890 +#define MPI_FCPORT10_EXT_OPTION1_TX_FAULT   (0x08)
1891 +#define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
1892 +#define MPI_FCPORT10_EXT_OPTION1_LOS        (0x02)
1893 +
1894 +
1895 +typedef struct _CONFIG_PAGE_FC_PORT_10
1896 +{
1897 +    CONFIG_PAGE_HEADER                          Header;             /* 00h */
1898 +    U8                                          Flags;              /* 04h */
1899 +    U8                                          Reserved1;          /* 05h */
1900 +    U16                                         Reserved2;          /* 06h */
1901 +    U32                                         HwConfig1;          /* 08h */
1902 +    U32                                         HwConfig2;          /* 0Ch */
1903 +    CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA        Base;               /* 10h */
1904 +    CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA    Extended;           /* 50h */
1905 +    U8                                          VendorSpecific[32]; /* 70h */
1906 +} CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
1907 +  FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
1908 +
1909 +#define MPI_FCPORTPAGE10_PAGEVERSION                    (0x01)
1910 +
1911 +/* standard MODDEF pin definitions (from GBIC spec.) */
1912 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK              (0x00000007)
1913 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF2                  (0x00000001)
1914 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF1                  (0x00000002)
1915 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF0                  (0x00000004)
1916 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC            (0x00000007)
1917 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX       (0x00000006)
1918 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER            (0x00000005)
1919 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW        (0x00000004)
1920 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM           (0x00000003)
1921 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL        (0x00000002)
1922 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW    (0x00000001)
1923 +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW    (0x00000000)
1924 +
1925 +#define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK               (0x00000010)
1926 +#define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK                (0x00000020)
1927 +
1928 +
1929 +/****************************************************************************
1930 +*   FC Device Config Pages
1931 +****************************************************************************/
1932 +
1933 +typedef struct _CONFIG_PAGE_FC_DEVICE_0
1934 +{
1935 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
1936 +    U64                     WWNN;                       /* 04h */
1937 +    U64                     WWPN;                       /* 0Ch */
1938 +    U32                     PortIdentifier;             /* 14h */
1939 +    U8                      Protocol;                   /* 18h */
1940 +    U8                      Flags;                      /* 19h */
1941 +    U16                     BBCredit;                   /* 1Ah */
1942 +    U16                     MaxRxFrameSize;             /* 1Ch */
1943 +    U8                      ADISCHardALPA;              /* 1Eh */
1944 +    U8                      PortNumber;                 /* 1Fh */
1945 +    U8                      FcPhLowestVersion;          /* 20h */
1946 +    U8                      FcPhHighestVersion;         /* 21h */
1947 +    U8                      CurrentTargetID;            /* 22h */
1948 +    U8                      CurrentBus;                 /* 23h */
1949 +} CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
1950 +  FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
1951 +
1952 +#define MPI_FC_DEVICE_PAGE0_PAGEVERSION                 (0x03)
1953 +
1954 +#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID    (0x01)
1955 +#define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID         (0x02)
1956 +#define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID          (0x04)
1957 +
1958 +#define MPI_FC_DEVICE_PAGE0_PROT_IP                     (0x01)
1959 +#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET             (0x02)
1960 +#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR          (0x04)
1961 +#define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY              (0x08)
1962 +
1963 +#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK      (MPI_FC_DEVICE_PGAD_PORT_MASK)
1964 +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK      (MPI_FC_DEVICE_PGAD_FORM_MASK)
1965 +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID  (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
1966 +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID   (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
1967 +#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK       (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
1968 +#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK       (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
1969 +#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT      (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
1970 +#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK       (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
1971 +
1972 +#define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN   (0xFF)
1973 +
1974 +/****************************************************************************
1975 +*   RAID Volume Config Pages
1976 +****************************************************************************/
1977 +
1978 +typedef struct _RAID_VOL0_PHYS_DISK
1979 +{
1980 +    U16                         Reserved;               /* 00h */
1981 +    U8                          PhysDiskMap;            /* 02h */
1982 +    U8                          PhysDiskNum;            /* 03h */
1983 +} RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
1984 +  RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
1985 +
1986 +#define MPI_RAIDVOL0_PHYSDISK_PRIMARY                   (0x01)
1987 +#define MPI_RAIDVOL0_PHYSDISK_SECONDARY                 (0x02)
1988 +
1989 +typedef struct _RAID_VOL0_STATUS
1990 +{
1991 +    U8                          Flags;                  /* 00h */
1992 +    U8                          State;                  /* 01h */
1993 +    U16                         Reserved;               /* 02h */
1994 +} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
1995 +  RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
1996 +
1997 +/* RAID Volume Page 0 VolumeStatus defines */
1998 +#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED                (0x01)
1999 +#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED               (0x02)
2000 +#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS     (0x04)
2001 +#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE        (0x08)
2002 +#define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL   (0x10)
2003 +
2004 +#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL               (0x00)
2005 +#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED              (0x01)
2006 +#define MPI_RAIDVOL0_STATUS_STATE_FAILED                (0x02)
2007 +#define MPI_RAIDVOL0_STATUS_STATE_MISSING               (0x03)
2008 +
2009 +typedef struct _RAID_VOL0_SETTINGS
2010 +{
2011 +    U16                         Settings;       /* 00h */
2012 +    U8                          HotSparePool;   /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2013 +    U8                          Reserved;       /* 02h */
2014 +} RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2015 +  RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2016 +
2017 +/* RAID Volume Page 0 VolumeSettings defines */
2018 +#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE       (0x0001)
2019 +#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART           (0x0002)
2020 +#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE             (0x0004)
2021 +#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC            (0x0008)
2022 +#define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102   (0x0020) /* obsolete */
2023 +#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX      (0x0010)
2024 +#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS               (0x8000)
2025 +
2026 +/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2027 +#define MPI_RAID_HOT_SPARE_POOL_0                       (0x01)
2028 +#define MPI_RAID_HOT_SPARE_POOL_1                       (0x02)
2029 +#define MPI_RAID_HOT_SPARE_POOL_2                       (0x04)
2030 +#define MPI_RAID_HOT_SPARE_POOL_3                       (0x08)
2031 +#define MPI_RAID_HOT_SPARE_POOL_4                       (0x10)
2032 +#define MPI_RAID_HOT_SPARE_POOL_5                       (0x20)
2033 +#define MPI_RAID_HOT_SPARE_POOL_6                       (0x40)
2034 +#define MPI_RAID_HOT_SPARE_POOL_7                       (0x80)
2035 +
2036 +/*
2037 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2038 + * one and check Header.PageLength at runtime.
2039 + */
2040 +#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2041 +#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX        (1)
2042 +#endif
2043 +
2044 +typedef struct _CONFIG_PAGE_RAID_VOL_0
2045 +{
2046 +    CONFIG_PAGE_HEADER      Header;         /* 00h */
2047 +    U8                      VolumeID;       /* 04h */
2048 +    U8                      VolumeBus;      /* 05h */
2049 +    U8                      VolumeIOC;      /* 06h */
2050 +    U8                      VolumeType;     /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2051 +    RAID_VOL0_STATUS        VolumeStatus;   /* 08h */
2052 +    RAID_VOL0_SETTINGS      VolumeSettings; /* 0Ch */
2053 +    U32                     MaxLBA;         /* 10h */
2054 +    U32                     Reserved1;      /* 14h */
2055 +    U32                     StripeSize;     /* 18h */
2056 +    U32                     Reserved2;      /* 1Ch */
2057 +    U32                     Reserved3;      /* 20h */
2058 +    U8                      NumPhysDisks;   /* 24h */
2059 +    U8                      DataScrubRate;  /* 25h */
2060 +    U8                      ResyncRate;     /* 26h */
2061 +    U8                      InactiveStatus; /* 27h */
2062 +    RAID_VOL0_PHYS_DISK     PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2063 +} CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2064 +  RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2065 +
2066 +#define MPI_RAIDVOLPAGE0_PAGEVERSION                    (0x05)
2067 +
2068 +/* values for RAID Volume Page 0 InactiveStatus field */
2069 +#define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE               (0x00)
2070 +#define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE        (0x01)
2071 +#define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE        (0x02)
2072 +#define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2073 +#define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE          (0x04)
2074 +#define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2075 +#define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED             (0x06)
2076 +
2077 +
2078 +typedef struct _CONFIG_PAGE_RAID_VOL_1
2079 +{
2080 +    CONFIG_PAGE_HEADER      Header;         /* 00h */
2081 +    U8                      VolumeID;       /* 01h */
2082 +    U8                      VolumeBus;      /* 02h */
2083 +    U8                      VolumeIOC;      /* 03h */
2084 +    U8                      Reserved0;      /* 04h */
2085 +    U8                      GUID[24];       /* 05h */
2086 +    U8                      Name[32];       /* 20h */
2087 +    U64                     WWID;           /* 40h */
2088 +    U32                     Reserved1;      /* 48h */
2089 +    U32                     Reserved2;      /* 4Ch */
2090 +} CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2091 +  RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2092 +
2093 +#define MPI_RAIDVOLPAGE1_PAGEVERSION                    (0x01)
2094 +
2095 +
2096 +/****************************************************************************
2097 +*   RAID Physical Disk Config Pages
2098 +****************************************************************************/
2099 +
2100 +typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2101 +{
2102 +    U8                      ErrorCdbByte;               /* 00h */
2103 +    U8                      ErrorSenseKey;              /* 01h */
2104 +    U16                     Reserved;                   /* 02h */
2105 +    U16                     ErrorCount;                 /* 04h */
2106 +    U8                      ErrorASC;                   /* 06h */
2107 +    U8                      ErrorASCQ;                  /* 07h */
2108 +    U16                     SmartCount;                 /* 08h */
2109 +    U8                      SmartASC;                   /* 0Ah */
2110 +    U8                      SmartASCQ;                  /* 0Bh */
2111 +} RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2112 +  RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2113 +
2114 +typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2115 +{
2116 +    U8                          VendorID[8];            /* 00h */
2117 +    U8                          ProductID[16];          /* 08h */
2118 +    U8                          ProductRevLevel[4];     /* 18h */
2119 +    U8                          Info[32];               /* 1Ch */
2120 +} RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2121 +  RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2122 +
2123 +typedef struct _RAID_PHYS_DISK0_SETTINGS
2124 +{
2125 +    U8              SepID;              /* 00h */
2126 +    U8              SepBus;             /* 01h */
2127 +    U8              HotSparePool;       /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2128 +    U8              PhysDiskSettings;   /* 03h */
2129 +} RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2130 +  RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2131 +
2132 +typedef struct _RAID_PHYS_DISK0_STATUS
2133 +{
2134 +    U8                              Flags;              /* 00h */
2135 +    U8                              State;              /* 01h */
2136 +    U16                             Reserved;           /* 02h */
2137 +} RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2138 +  RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2139 +
2140 +/* RAID Volume 2 IM Physical Disk DiskStatus flags */
2141 +
2142 +#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC           (0x01)
2143 +#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED              (0x02)
2144 +#define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME       (0x04)
2145 +#define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS      (0x00)
2146 +#define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS  (0x08)
2147 +
2148 +#define MPI_PHYSDISK0_STATUS_ONLINE                     (0x00)
2149 +#define MPI_PHYSDISK0_STATUS_MISSING                    (0x01)
2150 +#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE             (0x02)
2151 +#define MPI_PHYSDISK0_STATUS_FAILED                     (0x03)
2152 +#define MPI_PHYSDISK0_STATUS_INITIALIZING               (0x04)
2153 +#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED          (0x05)
2154 +#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED           (0x06)
2155 +#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE              (0xFF)
2156 +
2157 +typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2158 +{
2159 +    CONFIG_PAGE_HEADER              Header;             /* 00h */
2160 +    U8                              PhysDiskID;         /* 04h */
2161 +    U8                              PhysDiskBus;        /* 05h */
2162 +    U8                              PhysDiskIOC;        /* 06h */
2163 +    U8                              PhysDiskNum;        /* 07h */
2164 +    RAID_PHYS_DISK0_SETTINGS        PhysDiskSettings;   /* 08h */
2165 +    U32                             Reserved1;          /* 0Ch */
2166 +    U8                              ExtDiskIdentifier[8]; /* 10h */
2167 +    U8                              DiskIdentifier[16]; /* 18h */
2168 +    RAID_PHYS_DISK0_INQUIRY_DATA    InquiryData;        /* 28h */
2169 +    RAID_PHYS_DISK0_STATUS          PhysDiskStatus;     /* 64h */
2170 +    U32                             MaxLBA;             /* 68h */
2171 +    RAID_PHYS_DISK0_ERROR_DATA      ErrorData;          /* 6Ch */
2172 +} CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2173 +  RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2174 +
2175 +#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION           (0x02)
2176 +
2177 +
2178 +typedef struct _RAID_PHYS_DISK1_PATH
2179 +{
2180 +    U8                              PhysDiskID;         /* 00h */
2181 +    U8                              PhysDiskBus;        /* 01h */
2182 +    U16                             Reserved1;          /* 02h */
2183 +    U64                             WWID;               /* 04h */
2184 +    U64                             OwnerWWID;          /* 0Ch */
2185 +    U8                              OwnerIdentifier;    /* 14h */
2186 +    U8                              Reserved2;          /* 15h */
2187 +    U16                             Flags;              /* 16h */
2188 +} RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2189 +  RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2190 +
2191 +/* RAID Physical Disk Page 1 Flags field defines */
2192 +#define MPI_RAID_PHYSDISK1_FLAG_BROKEN          (0x0002)
2193 +#define MPI_RAID_PHYSDISK1_FLAG_INVALID         (0x0001)
2194 +
2195 +typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2196 +{
2197 +    CONFIG_PAGE_HEADER              Header;             /* 00h */
2198 +    U8                              NumPhysDiskPaths;   /* 04h */
2199 +    U8                              PhysDiskNum;        /* 05h */
2200 +    U16                             Reserved2;          /* 06h */
2201 +    U32                             Reserved1;          /* 08h */
2202 +    RAID_PHYS_DISK1_PATH            Path[1];            /* 0Ch */
2203 +} CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2204 +  RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2205 +
2206 +#define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION       (0x00)
2207 +
2208 +
2209 +/****************************************************************************
2210 +*   LAN Config Pages
2211 +****************************************************************************/
2212 +
2213 +typedef struct _CONFIG_PAGE_LAN_0
2214 +{
2215 +    ConfigPageHeader_t      Header;                     /* 00h */
2216 +    U16                     TxRxModes;                  /* 04h */
2217 +    U16                     Reserved;                   /* 06h */
2218 +    U32                     PacketPrePad;               /* 08h */
2219 +} CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
2220 +  LANPage0_t, MPI_POINTER pLANPage0_t;
2221 +
2222 +#define MPI_LAN_PAGE0_PAGEVERSION                       (0x01)
2223 +
2224 +#define MPI_LAN_PAGE0_RETURN_LOOPBACK                   (0x0000)
2225 +#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK                 (0x0001)
2226 +#define MPI_LAN_PAGE0_LOOPBACK_MASK                     (0x0001)
2227 +
2228 +typedef struct _CONFIG_PAGE_LAN_1
2229 +{
2230 +    ConfigPageHeader_t      Header;                     /* 00h */
2231 +    U16                     Reserved;                   /* 04h */
2232 +    U8                      CurrentDeviceState;         /* 06h */
2233 +    U8                      Reserved1;                  /* 07h */
2234 +    U32                     MinPacketSize;              /* 08h */
2235 +    U32                     MaxPacketSize;              /* 0Ch */
2236 +    U32                     HardwareAddressLow;         /* 10h */
2237 +    U32                     HardwareAddressHigh;        /* 14h */
2238 +    U32                     MaxWireSpeedLow;            /* 18h */
2239 +    U32                     MaxWireSpeedHigh;           /* 1Ch */
2240 +    U32                     BucketsRemaining;           /* 20h */
2241 +    U32                     MaxReplySize;               /* 24h */
2242 +    U32                     NegWireSpeedLow;            /* 28h */
2243 +    U32                     NegWireSpeedHigh;           /* 2Ch */
2244 +} CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2245 +  LANPage1_t, MPI_POINTER pLANPage1_t;
2246 +
2247 +#define MPI_LAN_PAGE1_PAGEVERSION                       (0x03)
2248 +
2249 +#define MPI_LAN_PAGE1_DEV_STATE_RESET                   (0x00)
2250 +#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL             (0x01)
2251 +
2252 +
2253 +/****************************************************************************
2254 +*   Inband Config Pages
2255 +****************************************************************************/
2256 +
2257 +typedef struct _CONFIG_PAGE_INBAND_0
2258 +{
2259 +    CONFIG_PAGE_HEADER      Header;                     /* 00h */
2260 +    MPI_VERSION_FORMAT      InbandVersion;              /* 04h */
2261 +    U16                     MaximumBuffers;             /* 08h */
2262 +    U16                     Reserved1;                  /* 0Ah */
2263 +} CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2264 +  InbandPage0_t, MPI_POINTER pInbandPage0_t;
2265 +
2266 +#define MPI_INBAND_PAGEVERSION          (0x00)
2267 +
2268 +
2269 +
2270 +/****************************************************************************
2271 +*   SAS IO Unit Config Pages
2272 +****************************************************************************/
2273 +
2274 +typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2275 +{
2276 +    U8          Port;                   /* 00h */
2277 +    U8          PortFlags;              /* 01h */
2278 +    U8          PhyFlags;               /* 02h */
2279 +    U8          NegotiatedLinkRate;     /* 03h */
2280 +    U32         ControllerPhyDeviceInfo;/* 04h */
2281 +    U16         AttachedDeviceHandle;   /* 08h */
2282 +    U16         ControllerDevHandle;    /* 0Ah */
2283 +    U32         DiscoveryStatus;        /* 0Ch */
2284 +} MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2285 +  SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2286 +
2287 +/*
2288 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2289 + * one and check Header.PageLength at runtime.
2290 + */
2291 +#ifndef MPI_SAS_IOUNIT0_PHY_MAX
2292 +#define MPI_SAS_IOUNIT0_PHY_MAX         (1)
2293 +#endif
2294 +
2295 +typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2296 +{
2297 +    CONFIG_EXTENDED_PAGE_HEADER     Header;                             /* 00h */
2298 +    U32                             Reserved1;                          /* 08h */
2299 +    U8                              NumPhys;                            /* 0Ch */
2300 +    U8                              Reserved2;                          /* 0Dh */
2301 +    U16                             Reserved3;                          /* 0Eh */
2302 +    MPI_SAS_IO_UNIT0_PHY_DATA       PhyData[MPI_SAS_IOUNIT0_PHY_MAX];   /* 10h */
2303 +} CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2304 +  SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2305 +
2306 +#define MPI_SASIOUNITPAGE0_PAGEVERSION      (0x03)
2307 +
2308 +/* values for SAS IO Unit Page 0 PortFlags */
2309 +#define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS    (0x08)
2310 +#define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM         (0x00)
2311 +#define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM         (0x04)
2312 +#define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG         (0x01)
2313 +
2314 +/* values for SAS IO Unit Page 0 PhyFlags */
2315 +#define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED              (0x04)
2316 +#define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT                 (0x02)
2317 +#define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT                 (0x01)
2318 +
2319 +/* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2320 +#define MPI_SAS_IOUNIT0_RATE_UNKNOWN                        (0x00)
2321 +#define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED                   (0x01)
2322 +#define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION       (0x02)
2323 +#define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE              (0x03)
2324 +#define MPI_SAS_IOUNIT0_RATE_1_5                            (0x08)
2325 +#define MPI_SAS_IOUNIT0_RATE_3_0                            (0x09)
2326 +
2327 +/* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2328 +
2329 +/* values for SAS IO Unit Page 0 DiscoveryStatus */
2330 +#define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
2331 +#define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
2332 +#define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
2333 +#define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR                     (0x00000008)
2334 +#define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
2335 +#define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
2336 +#define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
2337 +#define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
2338 +#define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
2339 +#define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
2340 +#define MPI_SAS_IOUNIT0_DS_TABLE_LINK                       (0x00000400)
2341 +#define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
2342 +#define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS                 (0x00001000)
2343 +
2344 +
2345 +typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2346 +{
2347 +    U8          Port;                   /* 00h */
2348 +    U8          PortFlags;              /* 01h */
2349 +    U8          PhyFlags;               /* 02h */
2350 +    U8          MaxMinLinkRate;         /* 03h */
2351 +    U32         ControllerPhyDeviceInfo;/* 04h */
2352 +    U32         Reserved1;              /* 08h */
2353 +} MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2354 +  SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2355 +
2356 +/*
2357 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2358 + * one and check Header.PageLength at runtime.
2359 + */
2360 +#ifndef MPI_SAS_IOUNIT1_PHY_MAX
2361 +#define MPI_SAS_IOUNIT1_PHY_MAX         (1)
2362 +#endif
2363 +
2364 +typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2365 +{
2366 +    CONFIG_EXTENDED_PAGE_HEADER Header;                             /* 00h */
2367 +    U16                         ControlFlags;                       /* 08h */
2368 +    U16                         MaxNumSATATargets;                  /* 0Ah */
2369 +    U32                         Reserved1;                          /* 0Ch */
2370 +    U8                          NumPhys;                            /* 10h */
2371 +    U8                          SATAMaxQDepth;                      /* 11h */
2372 +    U16                         Reserved2;                          /* 12h */
2373 +    MPI_SAS_IO_UNIT1_PHY_DATA   PhyData[MPI_SAS_IOUNIT1_PHY_MAX];   /* 14h */
2374 +} CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2375 +  SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2376 +
2377 +#define MPI_SASIOUNITPAGE1_PAGEVERSION      (0x04)
2378 +
2379 +/* values for SAS IO Unit Page 1 ControlFlags */
2380 +#define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST        (0x8000)
2381 +#define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX            (0x4000)
2382 +#define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX            (0x2000)
2383 +#define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE        (0x1000)
2384 +#define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH        (0x0800)
2385 +
2386 +#define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT        (0x0600)
2387 +#define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT       (9)
2388 +#define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH        (0x00)
2389 +#define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT         (0x01)
2390 +#define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT        (0x02)
2391 +
2392 +#define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2393 +#define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED     (0x0040)
2394 +#define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED       (0x0020)
2395 +#define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED       (0x0010)
2396 +#define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH   (0x0008)
2397 +#define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL     (0x0004)
2398 +#define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY     (0x0002)
2399 +#define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION       (0x0001)
2400 +
2401 +/* values for SAS IO Unit Page 1 PortFlags */
2402 +#define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM     (0x00)
2403 +#define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM     (0x04)
2404 +#define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG     (0x01)
2405 +
2406 +/* values for SAS IO Unit Page 0 PhyFlags */
2407 +#define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE           (0x04)
2408 +#define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT             (0x02)
2409 +#define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT             (0x01)
2410 +
2411 +/* values for SAS IO Unit Page 0 MaxMinLinkRate */
2412 +#define MPI_SAS_IOUNIT1_MAX_RATE_MASK                   (0xF0)
2413 +#define MPI_SAS_IOUNIT1_MAX_RATE_1_5                    (0x80)
2414 +#define MPI_SAS_IOUNIT1_MAX_RATE_3_0                    (0x90)
2415 +#define MPI_SAS_IOUNIT1_MIN_RATE_MASK                   (0x0F)
2416 +#define MPI_SAS_IOUNIT1_MIN_RATE_1_5                    (0x08)
2417 +#define MPI_SAS_IOUNIT1_MIN_RATE_3_0                    (0x09)
2418 +
2419 +/* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2420 +
2421 +
2422 +typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2423 +{
2424 +    CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2425 +    U32                                 Reserved1;              /* 08h */
2426 +    U16                                 MaxPersistentIDs;       /* 0Ch */
2427 +    U16                                 NumPersistentIDsUsed;   /* 0Eh */
2428 +    U8                                  Status;                 /* 10h */
2429 +    U8                                  Flags;                  /* 11h */
2430 +    U16                                 MaxNumPhysicalMappedIDs;/* 12h */              /* 12h */
2431 +} CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2432 +  SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2433 +
2434 +#define MPI_SASIOUNITPAGE2_PAGEVERSION      (0x04)
2435 +
2436 +/* values for SAS IO Unit Page 2 Status field */
2437 +#define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2438 +#define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS     (0x01)
2439 +
2440 +/* values for SAS IO Unit Page 2 Flags field */
2441 +#define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS   (0x01)
2442 +/* Physical Mapping Modes */
2443 +#define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE            (0x0E)
2444 +#define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE           (1)
2445 +#define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP                   (0x00)
2446 +#define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP        (0x01)
2447 +#define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP       (0x02)
2448 +
2449 +#define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT         (0x10)
2450 +#define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT              (0x20)
2451 +
2452 +
2453 +typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2454 +{
2455 +    CONFIG_EXTENDED_PAGE_HEADER Header;                         /* 00h */
2456 +    U32                         Reserved1;                      /* 08h */
2457 +    U32                         MaxInvalidDwordCount;           /* 0Ch */
2458 +    U32                         InvalidDwordCountTime;          /* 10h */
2459 +    U32                         MaxRunningDisparityErrorCount;  /* 14h */
2460 +    U32                         RunningDisparityErrorTime;      /* 18h */
2461 +    U32                         MaxLossDwordSynchCount;         /* 1Ch */
2462 +    U32                         LossDwordSynchCountTime;        /* 20h */
2463 +    U32                         MaxPhyResetProblemCount;        /* 24h */
2464 +    U32                         PhyResetProblemTime;            /* 28h */
2465 +} CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2466 +  SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2467 +
2468 +#define MPI_SASIOUNITPAGE3_PAGEVERSION      (0x00)
2469 +
2470 +
2471 +/****************************************************************************
2472 +*   SAS Expander Config Pages
2473 +****************************************************************************/
2474 +
2475 +typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2476 +{
2477 +    CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2478 +    U8                                  PhysicalPort;           /* 08h */
2479 +    U8                                  Reserved1;              /* 09h */
2480 +    U16                                 Reserved2;              /* 0Ah */
2481 +    U64                                 SASAddress;             /* 0Ch */
2482 +    U32                                 DiscoveryStatus;        /* 14h */
2483 +    U16                                 DevHandle;              /* 18h */
2484 +    U16                                 ParentDevHandle;        /* 1Ah */
2485 +    U16                                 ExpanderChangeCount;    /* 1Ch */
2486 +    U16                                 ExpanderRouteIndexes;   /* 1Eh */
2487 +    U8                                  NumPhys;                /* 20h */
2488 +    U8                                  SASLevel;               /* 21h */
2489 +    U8                                  Flags;                  /* 22h */
2490 +    U8                                  Reserved3;              /* 23h */
2491 +} CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2492 +  SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2493 +
2494 +#define MPI_SASEXPANDER0_PAGEVERSION        (0x02)
2495 +
2496 +/* values for SAS Expander Page 0 DiscoveryStatus field */
2497 +#define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED              (0x00000001)
2498 +#define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE       (0x00000002)
2499 +#define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS             (0x00000004)
2500 +#define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR               (0x00000008)
2501 +#define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT                (0x00000010)
2502 +#define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES          (0x00000020)
2503 +#define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST            (0x00000040)
2504 +#define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED        (0x00000080)
2505 +#define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR              (0x00000100)
2506 +#define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK           (0x00000200)
2507 +#define MPI_SAS_EXPANDER0_DS_TABLE_LINK                 (0x00000400)
2508 +#define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE         (0x00000800)
2509 +
2510 +/* values for SAS Expander Page 0 Flags field */
2511 +#define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG      (0x02)
2512 +#define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS      (0x01)
2513 +
2514 +
2515 +typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2516 +{
2517 +    CONFIG_EXTENDED_PAGE_HEADER Header;                 /* 00h */
2518 +    U8                          PhysicalPort;           /* 08h */
2519 +    U8                          Reserved1;              /* 09h */
2520 +    U16                         Reserved2;              /* 0Ah */
2521 +    U8                          NumPhys;                /* 0Ch */
2522 +    U8                          Phy;                    /* 0Dh */
2523 +    U16                         NumTableEntriesProgrammed; /* 0Eh */
2524 +    U8                          ProgrammedLinkRate;     /* 10h */
2525 +    U8                          HwLinkRate;             /* 11h */
2526 +    U16                         AttachedDevHandle;      /* 12h */
2527 +    U32                         PhyInfo;                /* 14h */
2528 +    U32                         AttachedDeviceInfo;     /* 18h */
2529 +    U16                         OwnerDevHandle;         /* 1Ch */
2530 +    U8                          ChangeCount;            /* 1Eh */
2531 +    U8                          NegotiatedLinkRate;     /* 1Fh */
2532 +    U8                          PhyIdentifier;          /* 20h */
2533 +    U8                          AttachedPhyIdentifier;  /* 21h */
2534 +    U8                          NumTableEntriesProg;    /* 22h */
2535 +    U8                          DiscoveryInfo;          /* 23h */
2536 +    U32                         Reserved3;              /* 24h */
2537 +} CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2538 +  SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2539 +
2540 +#define MPI_SASEXPANDER1_PAGEVERSION        (0x01)
2541 +
2542 +/* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2543 +
2544 +/* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2545 +
2546 +/* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2547 +
2548 +/* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2549 +
2550 +/* values for SAS Expander Page 1 DiscoveryInfo field */
2551 +#define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY DISABLED     (0x04)
2552 +#define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE   (0x02)
2553 +#define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES   (0x01)
2554 +
2555 +/* values for SAS Expander Page 1 NegotiatedLinkRate field */
2556 +#define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN              (0x00)
2557 +#define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED         (0x01)
2558 +#define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION   (0x02)
2559 +#define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE    (0x03)
2560 +#define MPI_SAS_EXPANDER1_NEG_RATE_1_5                  (0x08)
2561 +#define MPI_SAS_EXPANDER1_NEG_RATE_3_0                  (0x09)
2562 +
2563 +
2564 +/****************************************************************************
2565 +*   SAS Device Config Pages
2566 +****************************************************************************/
2567 +
2568 +typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2569 +{
2570 +    CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2571 +    U16                                 Slot;                   /* 08h */
2572 +    U16                                 EnclosureHandle;        /* 0Ah */
2573 +    U64                                 SASAddress;             /* 0Ch */
2574 +    U16                                 ParentDevHandle;        /* 14h */
2575 +    U8                                  PhyNum;                 /* 16h */
2576 +    U8                                  AccessStatus;           /* 17h */
2577 +    U16                                 DevHandle;              /* 18h */
2578 +    U8                                  TargetID;               /* 1Ah */
2579 +    U8                                  Bus;                    /* 1Bh */
2580 +    U32                                 DeviceInfo;             /* 1Ch */
2581 +    U16                                 Flags;                  /* 20h */
2582 +    U8                                  PhysicalPort;           /* 22h */
2583 +    U8                                  Reserved2;              /* 23h */
2584 +} CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2585 +  SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2586 +
2587 +#define MPI_SASDEVICE0_PAGEVERSION          (0x04)
2588 +
2589 +/* values for SAS Device Page 0 AccessStatus field */
2590 +#define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS               (0x00)
2591 +#define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED        (0x01)
2592 +#define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED  (0x02)
2593 +
2594 +/* values for SAS Device Page 0 Flags field */
2595 +#define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE          (0x0200)
2596 +#define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE        (0x0100)
2597 +#define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED  (0x0080)
2598 +#define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED      (0x0040)
2599 +#define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED        (0x0020)
2600 +#define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED        (0x0010)
2601 +#define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH      (0x0008)
2602 +#define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT        (0x0004)
2603 +#define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED             (0x0002)
2604 +#define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT            (0x0001)
2605 +
2606 +/* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2607 +
2608 +
2609 +typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2610 +{
2611 +    CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2612 +    U32                                 Reserved1;              /* 08h */
2613 +    U64                                 SASAddress;             /* 0Ch */
2614 +    U32                                 Reserved2;              /* 14h */
2615 +    U16                                 DevHandle;              /* 18h */
2616 +    U8                                  TargetID;               /* 1Ah */
2617 +    U8                                  Bus;                    /* 1Bh */
2618 +    U8                                  InitialRegDeviceFIS[20];/* 1Ch */
2619 +} CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2620 +  SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2621 +
2622 +#define MPI_SASDEVICE1_PAGEVERSION          (0x00)
2623 +
2624 +
2625 +typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2626 +{
2627 +    CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2628 +    U64                                 PhysicalIdentifier;     /* 08h */
2629 +    U32                                 EnclosureMapping;       /* 10h */
2630 +} CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2631 +  SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2632 +
2633 +#define MPI_SASDEVICE2_PAGEVERSION          (0x01)
2634 +
2635 +/* defines for SAS Device Page 2 EnclosureMapping field */
2636 +#define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT       (0x0000000F)
2637 +#define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT      (0)
2638 +#define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS           (0x000007F0)
2639 +#define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS          (4)
2640 +#define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX         (0x001FF800)
2641 +#define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX        (11)
2642 +
2643 +
2644 +/****************************************************************************
2645 +*   SAS PHY Config Pages
2646 +****************************************************************************/
2647 +
2648 +typedef struct _CONFIG_PAGE_SAS_PHY_0
2649 +{
2650 +    CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2651 +    U16                                 OwnerDevHandle;         /* 08h */
2652 +    U16                                 Reserved1;              /* 0Ah */
2653 +    U64                                 SASAddress;             /* 0Ch */
2654 +    U16                                 AttachedDevHandle;      /* 14h */
2655 +    U8                                  AttachedPhyIdentifier;  /* 16h */
2656 +    U8                                  Reserved2;              /* 17h */
2657 +    U32                                 AttachedDeviceInfo;     /* 18h */
2658 +    U8                                  ProgrammedLinkRate;     /* 20h */
2659 +    U8                                  HwLinkRate;             /* 21h */
2660 +    U8                                  ChangeCount;            /* 22h */
2661 +    U8                                  Flags;                  /* 23h */
2662 +    U32                                 PhyInfo;                /* 24h */
2663 +} CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2664 +  SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2665 +
2666 +#define MPI_SASPHY0_PAGEVERSION             (0x01)
2667 +
2668 +/* values for SAS PHY Page 0 ProgrammedLinkRate field */
2669 +#define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK                        (0xF0)
2670 +#define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE            (0x00)
2671 +#define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5                         (0x80)
2672 +#define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0                         (0x90)
2673 +#define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK                        (0x0F)
2674 +#define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE            (0x00)
2675 +#define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5                         (0x08)
2676 +#define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0                         (0x09)
2677 +
2678 +/* values for SAS PHY Page 0 HwLinkRate field */
2679 +#define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK                       (0xF0)
2680 +#define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5                        (0x80)
2681 +#define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0                        (0x90)
2682 +#define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK                       (0x0F)
2683 +#define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5                        (0x08)
2684 +#define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0                        (0x09)
2685 +
2686 +/* values for SAS PHY Page 0 Flags field */
2687 +#define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC              (0x01)
2688 +
2689 +/* values for SAS PHY Page 0 PhyInfo field */
2690 +#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE                   (0x00004000)
2691 +#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR                 (0x00002000)
2692 +#define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY                        (0x00001000)
2693 +
2694 +#define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME          (0x00000F00)
2695 +#define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME         (8)
2696 +
2697 +#define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE             (0x000000F0)
2698 +#define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING                     (0x00000000)
2699 +#define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING                (0x00000010)
2700 +#define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING                      (0x00000020)
2701 +
2702 +#define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE                     (0x0000000F)
2703 +#define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE                  (0x00000000)
2704 +#define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED                       (0x00000001)
2705 +#define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED                 (0x00000002)
2706 +#define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE                  (0x00000003)
2707 +#define MPI_SAS_PHY0_PHYINFO_RATE_1_5                           (0x00000008)
2708 +#define MPI_SAS_PHY0_PHYINFO_RATE_3_0                           (0x00000009)
2709 +
2710 +
2711 +typedef struct _CONFIG_PAGE_SAS_PHY_1
2712 +{
2713 +    CONFIG_EXTENDED_PAGE_HEADER Header;                     /* 00h */
2714 +    U32                         Reserved1;                  /* 08h */
2715 +    U32                         InvalidDwordCount;          /* 0Ch */
2716 +    U32                         RunningDisparityErrorCount; /* 10h */
2717 +    U32                         LossDwordSynchCount;        /* 14h */
2718 +    U32                         PhyResetProblemCount;       /* 18h */
2719 +} CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
2720 +  SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
2721 +
2722 +#define MPI_SASPHY1_PAGEVERSION             (0x00)
2723 +
2724 +
2725 +/****************************************************************************
2726 +*   SAS Enclosure Config Pages
2727 +****************************************************************************/
2728 +
2729 +typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
2730 +{
2731 +    CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2732 +    U32                                 Reserved1;              /* 08h */
2733 +    U64                                 EnclosureLogicalID;     /* 0Ch */
2734 +    U16                                 Flags;                  /* 14h */
2735 +    U16                                 EnclosureHandle;        /* 16h */
2736 +    U16                                 NumSlots;               /* 18h */
2737 +    U16                                 StartSlot;              /* 1Ah */
2738 +    U8                                  StartTargetID;          /* 1Ch */
2739 +    U8                                  StartBus;               /* 1Dh */
2740 +    U8                                  SEPTargetID;            /* 1Eh */
2741 +    U8                                  SEPBus;                 /* 1Fh */
2742 +    U32                                 Reserved2;              /* 20h */
2743 +    U32                                 Reserved3;              /* 24h */
2744 +} CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
2745 +  SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
2746 +
2747 +#define MPI_SASENCLOSURE0_PAGEVERSION       (0x01)
2748 +
2749 +/* values for SAS Enclosure Page 0 Flags field */
2750 +#define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID       (0x0020)
2751 +#define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID     (0x0010)
2752 +
2753 +#define MPI_SAS_ENCLS0_FLAGS_MNG_MASK               (0x000F)
2754 +#define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN            (0x0000)
2755 +#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES            (0x0001)
2756 +#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO          (0x0002)
2757 +#define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO          (0x0003)
2758 +#define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE      (0x0004)
2759 +#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO           (0x0005)
2760 +
2761 +
2762 +/****************************************************************************
2763 +*   Log Config Pages
2764 +****************************************************************************/
2765 +/*
2766 + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2767 + * one and check NumLogEntries at runtime.
2768 + */
2769 +#ifndef MPI_LOG_0_NUM_LOG_ENTRIES
2770 +#define MPI_LOG_0_NUM_LOG_ENTRIES        (1)
2771 +#endif
2772 +
2773 +#define MPI_LOG_0_LOG_DATA_LENGTH        (20)
2774 +
2775 +typedef struct _MPI_LOG_0_ENTRY
2776 +{
2777 +    U64         WWID;                               /* 00h */
2778 +    U32         TimeStamp;                          /* 08h */
2779 +    U32         Reserved1;                          /* 0Ch */
2780 +    U16         LogSequence;                        /* 10h */
2781 +    U16         LogEntryQualifier;                  /* 12h */
2782 +    U8          LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 14h */
2783 +} MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
2784 +  MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
2785 +
2786 +/* values for Log Page 0 LogEntry LogEntryQualifier field */
2787 +#define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED           (0x0000)
2788 +#define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET         (0x0001)
2789 +
2790 +typedef struct _CONFIG_PAGE_LOG_0
2791 +{
2792 +    CONFIG_EXTENDED_PAGE_HEADER Header;                     /* 00h */
2793 +    U32                         Reserved1;                  /* 08h */
2794 +    U32                         Reserved2;                  /* 0Ch */
2795 +    U16                         NumLogEntries;              /* 10h */
2796 +    U16                         Reserved3;                  /* 12h */
2797 +    MPI_LOG_0_ENTRY             LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
2798 +} CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
2799 +  LogPage0_t, MPI_POINTER pLogPage0_t;
2800 +
2801 +#define MPI_LOG_0_PAGEVERSION               (0x00)
2802 +
2803 +
2804 +#endif
2805 +
2806 diff -Nur mpt-status-1.2.0.orig/includes/mpi.h mpt-status-1.2.0/includes/mpi.h
2807 --- mpt-status-1.2.0.orig/includes/mpi.h        1970-01-01 01:00:00.000000000 +0100
2808 +++ mpt-status-1.2.0/includes/mpi.h     2011-09-11 17:15:29.689911532 +0200
2809 @@ -0,0 +1,789 @@
2810 +/*
2811 + *  Copyright (c) 2000-2005 LSI Logic Corporation.
2812 + *
2813 + *
2814 + *           Name:  mpi.h
2815 + *          Title:  MPI Message independent structures and definitions
2816 + *  Creation Date:  July 27, 2000
2817 + *
2818 + *    mpi.h Version:  01.05.08
2819 + *
2820 + *  Version History
2821 + *  ---------------
2822 + *
2823 + *  Date      Version   Description
2824 + *  --------  --------  ------------------------------------------------------
2825 + *  05-08-00  00.10.01  Original release for 0.10 spec dated 4/26/2000.
2826 + *  05-24-00  00.10.02  Added MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH definition.
2827 + *  06-06-00  01.00.01  Update MPI_VERSION_MAJOR and MPI_VERSION_MINOR.
2828 + *  06-22-00  01.00.02  Added MPI_IOCSTATUS_LAN_ definitions.
2829 + *                      Removed LAN_SUSPEND function definition.
2830 + *                      Added MPI_MSGFLAGS_CONTINUATION_REPLY definition.
2831 + *  06-30-00  01.00.03  Added MPI_CONTEXT_REPLY_TYPE_LAN definition.
2832 + *                      Added MPI_GET/SET_CONTEXT_REPLY_TYPE macros.
2833 + *  07-27-00  01.00.04  Added MPI_FAULT_ definitions.
2834 + *                      Removed MPI_IOCSTATUS_MSG/DATA_XFER_ERROR definitions.
2835 + *                      Added MPI_IOCSTATUS_INTERNAL_ERROR definition.
2836 + *                      Added MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH.
2837 + *  11-02-00  01.01.01  Original release for post 1.0 work.
2838 + *  12-04-00  01.01.02  Added new function codes.
2839 + *  01-09-01  01.01.03  Added more definitions to the system interface section
2840 + *                      Added MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT.
2841 + *  01-25-01  01.01.04  Changed MPI_VERSION_MINOR from 0x00 to 0x01.
2842 + *  02-20-01  01.01.05  Started using MPI_POINTER.
2843 + *                      Fixed value for MPI_DIAG_RW_ENABLE.
2844 + *                      Added defines for MPI_DIAG_PREVENT_IOC_BOOT and
2845 + *                      MPI_DIAG_CLEAR_FLASH_BAD_SIG.
2846 + *                      Obsoleted MPI_IOCSTATUS_TARGET_FC_ defines.
2847 + *  02-27-01  01.01.06  Removed MPI_HOST_INDEX_REGISTER define.
2848 + *                      Added function codes for RAID.
2849 + *  04-09-01  01.01.07  Added alternate define for MPI_DOORBELL_ACTIVE,
2850 + *                      MPI_DOORBELL_USED, to better match the spec.
2851 + *  08-08-01  01.02.01  Original release for v1.2 work.
2852 + *                      Changed MPI_VERSION_MINOR from 0x01 to 0x02.
2853 + *                      Added define MPI_FUNCTION_TOOLBOX.
2854 + *  09-28-01  01.02.02  New function code MPI_SCSI_ENCLOSURE_PROCESSOR.
2855 + *  11-01-01  01.02.03  Changed name to MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR.
2856 + *  03-14-02  01.02.04  Added MPI_HEADER_VERSION_ defines.
2857 + *  05-31-02  01.02.05  Bumped MPI_HEADER_VERSION_UNIT.
2858 + *  07-12-02  01.02.06  Added define for MPI_FUNCTION_MAILBOX.
2859 + *  09-16-02  01.02.07  Bumped value for MPI_HEADER_VERSION_UNIT.
2860 + *  11-15-02  01.02.08  Added define MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX and
2861 + *                      obsoleted define MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX.
2862 + *  04-01-03  01.02.09  New IOCStatus code: MPI_IOCSTATUS_FC_EXCHANGE_CANCELED
2863 + *  06-26-03  01.02.10  Bumped MPI_HEADER_VERSION_UNIT value.
2864 + *  01-16-04  01.02.11  Added define for MPI_IOCLOGINFO_TYPE_SHIFT.
2865 + *  04-29-04  01.02.12  Added function codes for MPI_FUNCTION_DIAG_BUFFER_POST
2866 + *                      and MPI_FUNCTION_DIAG_RELEASE.
2867 + *                      Added MPI_IOCSTATUS_DIAGNOSTIC_RELEASED define.
2868 + *                      Bumped MPI_HEADER_VERSION_UNIT value.
2869 + *  05-11-04  01.03.01  Bumped MPI_VERSION_MINOR for MPI v1.3.
2870 + *                      Added codes for Inband.
2871 + *  08-19-04  01.05.01  Added defines for Host Buffer Access Control doorbell.
2872 + *                      Added define for offset of High Priority Request Queue.
2873 + *                      Added new function codes and new IOCStatus codes.
2874 + *                      Added a IOCLogInfo type of SAS.
2875 + *  12-07-04  01.05.02  Bumped MPI_HEADER_VERSION_UNIT.
2876 + *  12-09-04  01.05.03  Bumped MPI_HEADER_VERSION_UNIT.
2877 + *  01-15-05  01.05.04  Bumped MPI_HEADER_VERSION_UNIT.
2878 + *  02-09-05  01.05.05  Bumped MPI_HEADER_VERSION_UNIT.
2879 + *  02-22-05  01.05.06  Bumped MPI_HEADER_VERSION_UNIT.
2880 + *  03-11-05  01.05.07  Removed function codes for SCSI IO 32 and
2881 + *                      TargetAssistExtended requests.
2882 + *                      Removed EEDP IOCStatus codes.
2883 + *  06-24-05  01.05.08  Added function codes for SCSI IO 32 and
2884 + *                      TargetAssistExtended requests.
2885 + *                      Added EEDP IOCStatus codes.
2886 + *  --------------------------------------------------------------------------
2887 + */
2888 +
2889 +#ifndef MPI_H
2890 +#define MPI_H
2891 +
2892 +
2893 +/*****************************************************************************
2894 +*
2895 +*        M P I    V e r s i o n    D e f i n i t i o n s
2896 +*
2897 +*****************************************************************************/
2898 +
2899 +#define MPI_VERSION_MAJOR                   (0x01)
2900 +#define MPI_VERSION_MINOR                   (0x05)
2901 +#define MPI_VERSION_MAJOR_MASK              (0xFF00)
2902 +#define MPI_VERSION_MAJOR_SHIFT             (8)
2903 +#define MPI_VERSION_MINOR_MASK              (0x00FF)
2904 +#define MPI_VERSION_MINOR_SHIFT             (0)
2905 +#define MPI_VERSION ((MPI_VERSION_MAJOR << MPI_VERSION_MAJOR_SHIFT) |   \
2906 +                                      MPI_VERSION_MINOR)
2907 +
2908 +#define MPI_VERSION_01_00                   (0x0100)
2909 +#define MPI_VERSION_01_01                   (0x0101)
2910 +#define MPI_VERSION_01_02                   (0x0102)
2911 +#define MPI_VERSION_01_03                   (0x0103)
2912 +#define MPI_VERSION_01_05                   (0x0105)
2913 +/* Note: The major versions of 0xe0 through 0xff are reserved */
2914 +
2915 +/* versioning for this MPI header set */
2916 +#define MPI_HEADER_VERSION_UNIT             (0x0A)
2917 +#define MPI_HEADER_VERSION_DEV              (0x00)
2918 +#define MPI_HEADER_VERSION_UNIT_MASK        (0xFF00)
2919 +#define MPI_HEADER_VERSION_UNIT_SHIFT       (8)
2920 +#define MPI_HEADER_VERSION_DEV_MASK         (0x00FF)
2921 +#define MPI_HEADER_VERSION_DEV_SHIFT        (0)
2922 +#define MPI_HEADER_VERSION ((MPI_HEADER_VERSION_UNIT << 8) | MPI_HEADER_VERSION_DEV)
2923 +
2924 +/*****************************************************************************
2925 +*
2926 +*        I O C    S t a t e    D e f i n i t i o n s
2927 +*
2928 +*****************************************************************************/
2929 +
2930 +#define MPI_IOC_STATE_RESET                 (0x00000000)
2931 +#define MPI_IOC_STATE_READY                 (0x10000000)
2932 +#define MPI_IOC_STATE_OPERATIONAL           (0x20000000)
2933 +#define MPI_IOC_STATE_FAULT                 (0x40000000)
2934 +
2935 +#define MPI_IOC_STATE_MASK                  (0xF0000000)
2936 +#define MPI_IOC_STATE_SHIFT                 (28)
2937 +
2938 +/* Fault state codes (product independent range 0x8000-0xFFFF) */
2939 +
2940 +#define MPI_FAULT_REQUEST_MESSAGE_PCI_PARITY_ERROR  (0x8111)
2941 +#define MPI_FAULT_REQUEST_MESSAGE_PCI_BUS_FAULT     (0x8112)
2942 +#define MPI_FAULT_REPLY_MESSAGE_PCI_PARITY_ERROR    (0x8113)
2943 +#define MPI_FAULT_REPLY_MESSAGE_PCI_BUS_FAULT       (0x8114)
2944 +#define MPI_FAULT_DATA_SEND_PCI_PARITY_ERROR        (0x8115)
2945 +#define MPI_FAULT_DATA_SEND_PCI_BUS_FAULT           (0x8116)
2946 +#define MPI_FAULT_DATA_RECEIVE_PCI_PARITY_ERROR     (0x8117)
2947 +#define MPI_FAULT_DATA_RECEIVE_PCI_BUS_FAULT        (0x8118)
2948 +
2949 +
2950 +/*****************************************************************************
2951 +*
2952 +*        P C I    S y s t e m    I n t e r f a c e    R e g i s t e r s
2953 +*
2954 +*****************************************************************************/
2955 +
2956 +/*
2957 + * Defines for working with the System Doorbell register.
2958 + * Values for doorbell function codes are included in the section that defines
2959 + * all the function codes (further on in this file).
2960 + */
2961 +#define MPI_DOORBELL_OFFSET                 (0x00000000)
2962 +#define MPI_DOORBELL_ACTIVE                 (0x08000000) /* DoorbellUsed */
2963 +#define MPI_DOORBELL_USED                   (MPI_DOORBELL_ACTIVE)
2964 +#define MPI_DOORBELL_ACTIVE_SHIFT           (27)
2965 +#define MPI_DOORBELL_WHO_INIT_MASK          (0x07000000)
2966 +#define MPI_DOORBELL_WHO_INIT_SHIFT         (24)
2967 +#define MPI_DOORBELL_FUNCTION_MASK          (0xFF000000)
2968 +#define MPI_DOORBELL_FUNCTION_SHIFT         (24)
2969 +#define MPI_DOORBELL_ADD_DWORDS_MASK        (0x00FF0000)
2970 +#define MPI_DOORBELL_ADD_DWORDS_SHIFT       (16)
2971 +#define MPI_DOORBELL_DATA_MASK              (0x0000FFFF)
2972 +#define MPI_DOORBELL_FUNCTION_SPECIFIC_MASK (0x0000FFFF)
2973 +
2974 +/* values for Host Buffer Access Control doorbell function */
2975 +#define MPI_DB_HPBAC_VALUE_MASK             (0x0000F000)
2976 +#define MPI_DB_HPBAC_ENABLE_ACCESS          (0x01)
2977 +#define MPI_DB_HPBAC_DISABLE_ACCESS         (0x02)
2978 +#define MPI_DB_HPBAC_FREE_BUFFER            (0x03)
2979 +
2980 +
2981 +#define MPI_WRITE_SEQUENCE_OFFSET           (0x00000004)
2982 +#define MPI_WRSEQ_KEY_VALUE_MASK            (0x0000000F)
2983 +#define MPI_WRSEQ_1ST_KEY_VALUE             (0x04)
2984 +#define MPI_WRSEQ_2ND_KEY_VALUE             (0x0B)
2985 +#define MPI_WRSEQ_3RD_KEY_VALUE             (0x02)
2986 +#define MPI_WRSEQ_4TH_KEY_VALUE             (0x07)
2987 +#define MPI_WRSEQ_5TH_KEY_VALUE             (0x0D)
2988 +
2989 +#define MPI_DIAGNOSTIC_OFFSET               (0x00000008)
2990 +#define MPI_DIAG_CLEAR_FLASH_BAD_SIG        (0x00000400)
2991 +#define MPI_DIAG_PREVENT_IOC_BOOT           (0x00000200)
2992 +#define MPI_DIAG_DRWE                       (0x00000080)
2993 +#define MPI_DIAG_FLASH_BAD_SIG              (0x00000040)
2994 +#define MPI_DIAG_RESET_HISTORY              (0x00000020)
2995 +#define MPI_DIAG_RW_ENABLE                  (0x00000010)
2996 +#define MPI_DIAG_RESET_ADAPTER              (0x00000004)
2997 +#define MPI_DIAG_DISABLE_ARM                (0x00000002)
2998 +#define MPI_DIAG_MEM_ENABLE                 (0x00000001)
2999 +
3000 +#define MPI_TEST_BASE_ADDRESS_OFFSET        (0x0000000C)
3001 +
3002 +#define MPI_DIAG_RW_DATA_OFFSET             (0x00000010)
3003 +
3004 +#define MPI_DIAG_RW_ADDRESS_OFFSET          (0x00000014)
3005 +
3006 +#define MPI_HOST_INTERRUPT_STATUS_OFFSET    (0x00000030)
3007 +#define MPI_HIS_IOP_DOORBELL_STATUS         (0x80000000)
3008 +#define MPI_HIS_REPLY_MESSAGE_INTERRUPT     (0x00000008)
3009 +#define MPI_HIS_DOORBELL_INTERRUPT          (0x00000001)
3010 +
3011 +#define MPI_HOST_INTERRUPT_MASK_OFFSET      (0x00000034)
3012 +#define MPI_HIM_RIM                         (0x00000008)
3013 +#define MPI_HIM_DIM                         (0x00000001)
3014 +
3015 +#define MPI_REQUEST_QUEUE_OFFSET            (0x00000040)
3016 +#define MPI_REQUEST_POST_FIFO_OFFSET        (0x00000040)
3017 +
3018 +#define MPI_REPLY_QUEUE_OFFSET              (0x00000044)
3019 +#define MPI_REPLY_POST_FIFO_OFFSET          (0x00000044)
3020 +#define MPI_REPLY_FREE_FIFO_OFFSET          (0x00000044)
3021 +
3022 +#define MPI_HI_PRI_REQUEST_QUEUE_OFFSET     (0x00000048)
3023 +
3024 +
3025 +
3026 +/*****************************************************************************
3027 +*
3028 +*        M e s s a g e    F r a m e    D e s c r i p t o r s
3029 +*
3030 +*****************************************************************************/
3031 +
3032 +#define MPI_REQ_MF_DESCRIPTOR_NB_MASK       (0x00000003)
3033 +#define MPI_REQ_MF_DESCRIPTOR_F_BIT         (0x00000004)
3034 +#define MPI_REQ_MF_DESCRIPTOR_ADDRESS_MASK  (0xFFFFFFF8)
3035 +
3036 +#define MPI_ADDRESS_REPLY_A_BIT             (0x80000000)
3037 +#define MPI_ADDRESS_REPLY_ADDRESS_MASK      (0x7FFFFFFF)
3038 +
3039 +#define MPI_CONTEXT_REPLY_A_BIT             (0x80000000)
3040 +#define MPI_CONTEXT_REPLY_TYPE_MASK         (0x60000000)
3041 +#define MPI_CONTEXT_REPLY_TYPE_SCSI_INIT    (0x00)
3042 +#define MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET  (0x01)
3043 +#define MPI_CONTEXT_REPLY_TYPE_LAN          (0x02)
3044 +#define MPI_CONTEXT_REPLY_TYPE_SHIFT        (29)
3045 +#define MPI_CONTEXT_REPLY_CONTEXT_MASK      (0x1FFFFFFF)
3046 +
3047 +
3048 +/****************************************************************************/
3049 +/* Context Reply macros                                                     */
3050 +/****************************************************************************/
3051 +
3052 +#define MPI_GET_CONTEXT_REPLY_TYPE(x)  (((x) & MPI_CONTEXT_REPLY_TYPE_MASK) \
3053 +                                          >> MPI_CONTEXT_REPLY_TYPE_SHIFT)
3054 +
3055 +#define MPI_SET_CONTEXT_REPLY_TYPE(x, typ)                                  \
3056 +            ((x) = ((x) & ~MPI_CONTEXT_REPLY_TYPE_MASK) |                   \
3057 +                            (((typ) << MPI_CONTEXT_REPLY_TYPE_SHIFT) &      \
3058 +                                        MPI_CONTEXT_REPLY_TYPE_MASK))
3059 +
3060 +
3061 +/*****************************************************************************
3062 +*
3063 +*        M e s s a g e    F u n c t i o n s
3064 +*              0x80 -> 0x8F reserved for private message use per product
3065 +*
3066 +*
3067 +*****************************************************************************/
3068 +
3069 +#define MPI_FUNCTION_SCSI_IO_REQUEST                (0x00)
3070 +#define MPI_FUNCTION_SCSI_TASK_MGMT                 (0x01)
3071 +#define MPI_FUNCTION_IOC_INIT                       (0x02)
3072 +#define MPI_FUNCTION_IOC_FACTS                      (0x03)
3073 +#define MPI_FUNCTION_CONFIG                         (0x04)
3074 +#define MPI_FUNCTION_PORT_FACTS                     (0x05)
3075 +#define MPI_FUNCTION_PORT_ENABLE                    (0x06)
3076 +#define MPI_FUNCTION_EVENT_NOTIFICATION             (0x07)
3077 +#define MPI_FUNCTION_EVENT_ACK                      (0x08)
3078 +#define MPI_FUNCTION_FW_DOWNLOAD                    (0x09)
3079 +#define MPI_FUNCTION_TARGET_CMD_BUFFER_POST         (0x0A)
3080 +#define MPI_FUNCTION_TARGET_ASSIST                  (0x0B)
3081 +#define MPI_FUNCTION_TARGET_STATUS_SEND             (0x0C)
3082 +#define MPI_FUNCTION_TARGET_MODE_ABORT              (0x0D)
3083 +#define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST          (0x0E)
3084 +#define MPI_FUNCTION_FC_LINK_SRVC_RSP               (0x0F)
3085 +#define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND           (0x10)
3086 +#define MPI_FUNCTION_FC_ABORT                       (0x11)
3087 +#define MPI_FUNCTION_FW_UPLOAD                      (0x12)
3088 +#define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND       (0x13)
3089 +#define MPI_FUNCTION_FC_PRIMITIVE_SEND              (0x14)
3090 +
3091 +#define MPI_FUNCTION_RAID_ACTION                    (0x15)
3092 +#define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH       (0x16)
3093 +
3094 +#define MPI_FUNCTION_TOOLBOX                        (0x17)
3095 +
3096 +#define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR       (0x18)
3097 +
3098 +#define MPI_FUNCTION_MAILBOX                        (0x19)
3099 +
3100 +#define MPI_FUNCTION_SMP_PASSTHROUGH                (0x1A)
3101 +#define MPI_FUNCTION_SAS_IO_UNIT_CONTROL            (0x1B)
3102 +#define MPI_FUNCTION_SATA_PASSTHROUGH               (0x1C)
3103 +
3104 +#define MPI_FUNCTION_DIAG_BUFFER_POST               (0x1D)
3105 +#define MPI_FUNCTION_DIAG_RELEASE                   (0x1E)
3106 +
3107 +#define MPI_FUNCTION_SCSI_IO_32                     (0x1F)
3108 +
3109 +#define MPI_FUNCTION_LAN_SEND                       (0x20)
3110 +#define MPI_FUNCTION_LAN_RECEIVE                    (0x21)
3111 +#define MPI_FUNCTION_LAN_RESET                      (0x22)
3112 +
3113 +#define MPI_FUNCTION_TARGET_ASSIST_EXTENDED         (0x23)
3114 +#define MPI_FUNCTION_TARGET_CMD_BUF_BASE_POST       (0x24)
3115 +#define MPI_FUNCTION_TARGET_CMD_BUF_LIST_POST       (0x25)
3116 +
3117 +#define MPI_FUNCTION_INBAND_BUFFER_POST             (0x28)
3118 +#define MPI_FUNCTION_INBAND_SEND                    (0x29)
3119 +#define MPI_FUNCTION_INBAND_RSP                     (0x2A)
3120 +#define MPI_FUNCTION_INBAND_ABORT                   (0x2B)
3121 +
3122 +#define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET         (0x40)
3123 +#define MPI_FUNCTION_IO_UNIT_RESET                  (0x41)
3124 +#define MPI_FUNCTION_HANDSHAKE                      (0x42)
3125 +#define MPI_FUNCTION_REPLY_FRAME_REMOVAL            (0x43)
3126 +#define MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL    (0x44)
3127 +
3128 +
3129 +/* standard version format */
3130 +typedef struct _MPI_VERSION_STRUCT
3131 +{
3132 +    U8                      Dev;                        /* 00h */
3133 +    U8                      Unit;                       /* 01h */
3134 +    U8                      Minor;                      /* 02h */
3135 +    U8                      Major;                      /* 03h */
3136 +} MPI_VERSION_STRUCT, MPI_POINTER PTR_MPI_VERSION_STRUCT,
3137 +  MpiVersionStruct_t, MPI_POINTER pMpiVersionStruct;
3138 +
3139 +typedef union _MPI_VERSION_FORMAT
3140 +{
3141 +    MPI_VERSION_STRUCT      Struct;
3142 +    U32                     Word;
3143 +} MPI_VERSION_FORMAT, MPI_POINTER PTR_MPI_VERSION_FORMAT,
3144 +  MpiVersionFormat_t, MPI_POINTER pMpiVersionFormat_t;
3145 +
3146 +
3147 +/*****************************************************************************
3148 +*
3149 +*        S c a t t e r    G a t h e r    E l e m e n t s
3150 +*
3151 +*****************************************************************************/
3152 +
3153 +/****************************************************************************/
3154 +/*  Simple element structures                                               */
3155 +/****************************************************************************/
3156 +
3157 +typedef struct _SGE_SIMPLE32
3158 +{
3159 +    U32                     FlagsLength;
3160 +    U32                     Address;
3161 +} SGE_SIMPLE32, MPI_POINTER PTR_SGE_SIMPLE32,
3162 +  SGESimple32_t, MPI_POINTER pSGESimple32_t;
3163 +
3164 +typedef struct _SGE_SIMPLE64
3165 +{
3166 +    U32                     FlagsLength;
3167 +    U64                     Address;
3168 +} SGE_SIMPLE64, MPI_POINTER PTR_SGE_SIMPLE64,
3169 +  SGESimple64_t, MPI_POINTER pSGESimple64_t;
3170 +
3171 +typedef struct _SGE_SIMPLE_UNION
3172 +{
3173 +    U32                     FlagsLength;
3174 +    union
3175 +    {
3176 +        U32                 Address32;
3177 +        U64                 Address64;
3178 +    }u;
3179 +} SGE_SIMPLE_UNION, MPI_POINTER PTR_SGE_SIMPLE_UNION,
3180 +  SGESimpleUnion_t, MPI_POINTER pSGESimpleUnion_t;
3181 +
3182 +/****************************************************************************/
3183 +/*  Chain element structures                                                */
3184 +/****************************************************************************/
3185 +
3186 +typedef struct _SGE_CHAIN32
3187 +{
3188 +    U16                     Length;
3189 +    U8                      NextChainOffset;
3190 +    U8                      Flags;
3191 +    U32                     Address;
3192 +} SGE_CHAIN32, MPI_POINTER PTR_SGE_CHAIN32,
3193 +  SGEChain32_t, MPI_POINTER pSGEChain32_t;
3194 +
3195 +typedef struct _SGE_CHAIN64
3196 +{
3197 +    U16                     Length;
3198 +    U8                      NextChainOffset;
3199 +    U8                      Flags;
3200 +    U64                     Address;
3201 +} SGE_CHAIN64, MPI_POINTER PTR_SGE_CHAIN64,
3202 +  SGEChain64_t, MPI_POINTER pSGEChain64_t;
3203 +
3204 +typedef struct _SGE_CHAIN_UNION
3205 +{
3206 +    U16                     Length;
3207 +    U8                      NextChainOffset;
3208 +    U8                      Flags;
3209 +    union
3210 +    {
3211 +        U32                 Address32;
3212 +        U64                 Address64;
3213 +    }u;
3214 +} SGE_CHAIN_UNION, MPI_POINTER PTR_SGE_CHAIN_UNION,
3215 +  SGEChainUnion_t, MPI_POINTER pSGEChainUnion_t;
3216 +
3217 +/****************************************************************************/
3218 +/*  Transaction Context element                                             */
3219 +/****************************************************************************/
3220 +
3221 +typedef struct _SGE_TRANSACTION32
3222 +{
3223 +    U8                      Reserved;
3224 +    U8                      ContextSize;
3225 +    U8                      DetailsLength;
3226 +    U8                      Flags;
3227 +    U32                     TransactionContext[1];
3228 +    U32                     TransactionDetails[1];
3229 +} SGE_TRANSACTION32, MPI_POINTER PTR_SGE_TRANSACTION32,
3230 +  SGETransaction32_t, MPI_POINTER pSGETransaction32_t;
3231 +
3232 +typedef struct _SGE_TRANSACTION64
3233 +{
3234 +    U8                      Reserved;
3235 +    U8                      ContextSize;
3236 +    U8                      DetailsLength;
3237 +    U8                      Flags;
3238 +    U32                     TransactionContext[2];
3239 +    U32                     TransactionDetails[1];
3240 +} SGE_TRANSACTION64, MPI_POINTER PTR_SGE_TRANSACTION64,
3241 +  SGETransaction64_t, MPI_POINTER pSGETransaction64_t;
3242 +
3243 +typedef struct _SGE_TRANSACTION96
3244 +{
3245 +    U8                      Reserved;
3246 +    U8                      ContextSize;
3247 +    U8                      DetailsLength;
3248 +    U8                      Flags;
3249 +    U32                     TransactionContext[3];
3250 +    U32                     TransactionDetails[1];
3251 +} SGE_TRANSACTION96, MPI_POINTER PTR_SGE_TRANSACTION96,
3252 +  SGETransaction96_t, MPI_POINTER pSGETransaction96_t;
3253 +
3254 +typedef struct _SGE_TRANSACTION128
3255 +{
3256 +    U8                      Reserved;
3257 +    U8                      ContextSize;
3258 +    U8                      DetailsLength;
3259 +    U8                      Flags;
3260 +    U32                     TransactionContext[4];
3261 +    U32                     TransactionDetails[1];
3262 +} SGE_TRANSACTION128, MPI_POINTER PTR_SGE_TRANSACTION128,